Sajid Gul Khawaja

Crackle separation and classification from normal Respiratory sounds using Gaussian Mixture Model

Analysis of Respiratory sound signal is helpful in detection of adventitious lung sound which are an indication of disease. This helps in classification of normal respiratory sounds from abnormal respiratory sounds and this can be used to accurately diagnose respiratory diseases as is done by a medical practitioner via auscultation. This process has subjective nature and that is why simple auscultation cannot be relied upon. A computer aided diagnostic system which analyzes respiratory sounds can be very helpful in detection of various respiratory diseases such as pneumonia, asthma, bronchitis and tuberculosis. In this paper we present a novel method for automated detection of crackles which indicate severity of a respiratory disease. The proposed system consists of four modules i.e., pre-processing in which noise is filtered out, followed by feature extraction. The proposed system then performs feature selection based on rank tests and finally classification to separate crackles from normal breath sounds.

A novel multiprocessor architecture for k-means clustering algorithm based on network-on-chip

The k-means clustering is one of the widely used algorithms in Data Mining and Machine Learning domains due to the simplicity, efficiency and scalability involved. The algorithm allocates N data-points or samples to k-clusters employing the minimum distances from respective cluster centroids. Distance calculation is intrinsically a computationally intensive task which is usually accelerated by using specific hardware platforms like Field Programmable Gate Arrays (FPGAs) and Graphic Processing Unit (GPUs) etc. Hardware implementations absolve k-means from these exhaustive computations by using the inherent parallelism of the k-means clustering technique. In this paper we propose a Multi-Processor based sequentially unfolded architecture for k-means clustering using N-tiles in a collaborative working environment. The tiles work independently in parallel and largely interchange data at the end of iteration. In proposed framework the exchange of data between titles is carried out using a Network-on-Chip (NoC) inter-connect to elevate communication bottleneck caused by concurrent working of tiles. The modularity of the proposed model permits scalability with respect to the number of working tiles. The performance evaluation of proposed architecture is done using Speed, Area and average Throughput.

Parallel architecture for implementation of frequent itemset mining using FP-growth

Frequent itemset mining is a fundamental step in analysis of big data where correlation among the raw data in deemed necessary. In modern era the amount of data available for processing has grown exponentially, making it a stepper task for mining algorithms to provide solution in a timely manner. The software implementations are normally not efficient in handling such datasets thus focus on parallel architecture seems imminent. In this paper we propose a Multi-Processor based sequentially unfolded architecture for implementation of FP-Growth algorithm. The proposed framework exploits the inherent parallelism available in the FP-Growth algorithm such that N-processing entities (PEs) can work in a collaborative environment. The processing entities work in an independent manner in parallel and largely interchange data at the close of each iteration. The overall architecture is modular which permits scalability of the design with regards to the number of parallel processing entities. The performance of the framework is evaluated using benchmark datasets and their results show a linear increase in the speedup of our proposed framework with increase in PEs.

Multicore Framework for Finding Frequent Item-Sets Using TDS

Mining of frequent items from a dataset is a prime problem in the field of data mining. It plays a pivotal role in many of the data mining applications. In recent years, technological improvements have provided us with cheaper storage spaces capable of handling gigantic amount of digital data of human activities. This humongous data becomes a bottleneck for data analysts as mining algorithms often suffer from performance issues while running larger datasets or where number of items become very large. In this paper, we propose a novel tree based data structure (TDS) for saving itemsets as candidates for time effective application of Apriori property for pruning. The TD structure shows significant improvement in timing as compared to traditional structure. Furthermore, we propose a multicore framework for the processing of TDS based Apriori Algorithm. The framework is based on divide and conquer approach, where all cores work in parallel on their allocated subset of data. Each core shares their local results with other cores to get the global results leading to a collaborative working environment. The proposed framework is highly scalable which requires no change in the overall working of the algorithm. In order to thoroughly test the proposed framework, experimentation is performed using 4 benchmark datasets and its evaluation is carried out on the bases of number of cycles, execution time and comparative speedup. The results indicate that TDS is significantly faster and while working with multicore framework a direct relationship exists in speedup for all datsets with the number of working cores.

Network-on-Chip based MPSoC architecture for k-mean clustering algorithm

Data and image segmentation plays pivotal role in the application of machine learning. k-means, as a tool for unsupervised clustering, is a widely used algorithm for segmentation due to its inherent simplicity and efficiency. k-means partitions datasets into subsets based on their fitness value. As such k-means is a well suited algorithm for implementation on hardware platform such as Field Programmable Gate Array (FPGA) but requires high computation time. Hardware accelerators can help in reducing the computation complexity of the algorithm. In this paper, we present a simplified multicore based scalable hardware architecture for implementation of k-means. Mean and fitness modules in proposed architecture are further unfolded to further enhance the speed of k-means clustering algorithm. The unfolding factor has to be selected by keeping the area of the target device in check. In the proposed architecture, the cores are further connected through Network on Chip (NoC) interconnect network which allows for higher scalability while elevating the bottleneck of message passing. The performance of our MPSoC architecture has been evaluated with respect to Average Speedup, Average Throughput and Area consumption with and without use of NoC interconnect. Finally, we compare the use of different NoC interconnect models with respect to maximum Operating Frequency, average Throughput and Area overhead.

Analysis of EEG Signals for Detection of Epileptic Seizure Using Hybrid Feature Set

Epileptic Seizures occur as a result of certain electrical action in the brain. This makes the patient behave abnormally for a limited amount of time. The electrical activity can be measured with the help electrodes attached to different areas of the scalp to capture the EEG signals. Usually, the signals from the aforementioned device are interpreted by the specialists who specialize in this very thing but their detection is susceptible to errors which prove fatal in some cases. This paper provides an automated system which will detect epileptic seizure without involving an expert opinion. The proposed system goes through a four step process i.e. pre-processing, where the data is organized to suit the system processing and noise is removed. Then temporal and spectral feature extraction is performed. The system then applies the feature selection procedure to extract best set of features which are finally passed to the next phase for classification of EEG signals as normal or abnormal. The suggested system is established on a publicly open dataset and provides an average accuracy of 86.93 %.

Analysis of PCG signals using quality assessment and homomorphic filters for localization and classification of heart sounds

BACKGROUND AND OBJECTIVE Accurate localization of heart beats in phonocardiogram (PCG) signal is very crucial for correct segmentation and classification of heart sounds into S1 and S2. This task becomes challenging due to inclusion of noise in acquisition process owing to number of different factors. In this paper we propose a system for heart sound localization and classification into S1 and S2. The proposed system introduces the concept of quality assessment before localization, feature extraction and classification of heart sounds. METHODS The signal quality is assessed by predefined criteria based upon number of peaks and zero crossing of PCG signal. Once quality assessment is performed, then heart beats within PCG signal are localized, which is done by envelope extraction using homomorphic envelogram and finding prominent peaks. In order to classify localized peaks into S1 and S2, temporal and time-frequency based statistical features have been used. Support Vector Machine using radial basis function kernel is used for classification of heart beats into S1 and S2 based upon extracted features. The performance of the proposed system is evaluated using Accuracy, Sensitivity, Specificity, F-measure and Total Error. The dataset provided by PASCAL classifying heart sound challenge is used for testing. RESULTS Performance of system is significantly improved by quality assessment. Results shows that proposed Localization algorithm achieves accuracy up to 97% and generates smallest total average error among top 3 challenge participants. The classification algorithm achieves accuracy up to 91%. CONCLUSION The system provides firm foundation for the detection of normal and abnormal heart sounds for cardiovascular disease detection.

A surrogate channel based analysis of EEG signals for detection of epileptic seizure

The human brain produces electrical signals which prove vital in understanding the degree of abnormality that may, in many cases, result in a person behaving unusually. Epileptic seizures are known to be sudden surges of electrical activity in the brain which cause the affected person to behave abnormally for a short time period. The information contained in these signals is recorded via an EEG machine. Traditionally, these signals are interpreted by specialist neurologists. This technique, however, induces the human error into the observation which may cause fatal damage. This research presents an autonomous system, capable of detecting the occurrence of an epileptic seizure, without the help of a specialist. The solution presented in this study consists of four steps i.e. pre-processing, feature extraction, feature selection and classification. The purpose of pre-processing is to organize the data in an orderly manner and to remove noise. We have also applied Laplacian smoothing on multichannel data to generate a surrogate channel having information of all channels. The feature extraction phase extracts temporal, spectral and time-spectral domain features for proper representation of seizure and non-seizure samples. The phase is followed by the process of feature selection, where the best set of features are determined using rank features and are finally used to classify input EEG signals as normal or abnormal using a hybrid classifier. The proposed system is tested on a publicly available dataset and results show the significance of the proposed system.

A novel mean-shift architecture for scalable multiprocessor implementation

Organizing data into its natural grouping based on intrinsic characteristics is the most sensible thing to do with unlabeled data. Mean shift is a non-parametric mode seeking algorithm widely used for data clustering, image segmentation and object tracking, but its use in real time applications is limited because of its high computational cost. In this paper we propose a hybrid, sequentially unfolded, model for the implementation of mean shift clustering algorithm targeting Hardware Platforms. The proposed model uses multiple processors working in parallel on independent data allowing faster convergence of the algorithm. The model also supports scalability with respect to total number of working processors. Experimentation has yielded that computational cost decreases exponentially in each iteration. The proposed model can be implemented on any hardware which can support parallel architecture. Finally, it is also shown that hardware implementation will give same results as its software implementation.

A Novel Architecture for k-means Clustering Algorithm

Technological advancements in todays information age has helped the researchers to capture digital footprints of humans with regards to their daily activities. These logs of information posses valuable information for the data analytics who process it to find hidden pattern and unique behavior. Among the many algorithms k-means clustering is one of the very popular and widely used algorithm in the field of data mining and machine learning. k-means provides natural segments of dataset provided for clustering. It uses proximity to assign data points to a specific cluster, here the criteria of allocation is the minimum distance from the cluster center. Unfortunately, the rate of data growth has not been met by the speed of the algorithms. A number of hardware based solutions have been proposed to increase the processing power of different algorithms. In this paper, we present a novel algorithm for k-mean clustering which exploits the data redundancy occurring in the dataset. The proposed algorithm performs computations for the available unique items in the dataset and uses its frequency to finalize the results. Furthermore, FPGA based hardware architecture for the proposed algorithm is also presented in the paper. The performance of the proposed algorithm and its hardware implementation is evaluated using execution time, speedup and throughput. The proposed architecture provides speedup of 23 times and 2600 times against sequential hardware architecture and software implementation with a very small area requirement.