Salvador H. Talisa

Impact of Decorrelation Techniques on Sampling Noise in Radio-Frequency Applications

Analog-to-digital converter (ADC) noise limits the dynamic range of many radio-frequency systems for test and measurement, sensor, and communications applications. Improvements in the total dynamic range (as measured by the SNR) can be achieved by combining M ADCs in parallel, yielding an increase in SNR of M if the noise is fully uncorrelated across ADC units. However, the presence of correlated noise will limit the SNR improvement to a factor less than M. Noise in an ADC is due to thermal processes, quantization, and clock jitter. In an array of ADCs, thermal and quantization noise are independently generated in each ADC, but if a common clock is used, its jitter will generate correlated sampling noise in all the ADCs in the array. In this paper, we analyze and experimentally measure the impact of previously proposed harmonic decorrelation techniques on the sampling noise of an array of parallel ADCs driven by a common clock, sampling at an intermediate frequency. Both theory and experiments reveal that the decorrelation techniques reduce the total sampling noise by half, which is a result that could substantially relax clock requirements for high-dynamic-range systems and thus reduce clock costs.

Benefits of Digital Phased Array Radars

In this paper, an overview is given of the radar benefits of digital arrays in comparison with conventional phased arrays. Considered are passive and active phased arrays as well as subarray- and element-level digital arrays; their key differences are highlighted. A discussion of several radar attributes and performance measures follows to show the advantages and promise of element-level digital arrays as the newest generation architecture for radar and other electronic systems. Radar attributes considered are antenna patterns and beam control (including adaptive interference cancellation), dynamic range, in-band linearity, system phase noise, and angle measurement accuracy.

High-Dynamic-Range Receivers for Digital Beam Forming Radar Systems

A microwave S-band receiver was developed for studying dynamic range issues in digital beam forming (DBF), phased-array radar systems with multiple receivers. Particular attention was paid to understanding the balance between the analog and the analog-digital conversion segments of the receiver to maximize its dynamic range. Measurements of spurious signals were made well below the receiver noise floor to gain an understanding of which spurs, if correlated among the receivers in a DBF system, might appear above the noise level at the output of the digital beam former.

Simultaneous digital measurement of phase and amplitude noise

In this article, we describe the simultaneous digital measurement of both phase (PM) and amplitude (AM) noise of VHF and microwave sources by the direct digitization of the signal-under-test. Our measurement approach takes advantage of a commercially-available, high-dynamic-range analog-to-digital converter driven by a high-performance clock to digitize the signal-under-test with high fidelity. Following digitization, phase and amplitude fluctuations are extracted and converted to PM and AM noise spectra. Measurement of microwave signals is accomplished by the inclusion of a specially-designed low-noise down-converter to translate the signal frequency to the VHF regime while introducing minimal additional signal noise. Measurements made on this system are shown to be in good agreement with those obtained using a conventional heterodyne mixer system. In addition to speeding the characterization of RF sources by simultaneously measuring both PM and AM signal characteristics, the digital noise measurement approach allows the direct measurement of the PM- and AM-noise spectra of more complex signals, such as pulsed CW waveforms, in both the VHF and microwave regimes.

Effects of channel mismatch and phase noise on jamming cancellation

Various hardware errors, including channel mismatch and phase noise, adversely affect the performance of jamming sidelobe cancellation in a digital beamforming array that combines array elements into overlapped subarrays for digital combining and uses auxiliary channels to obtain an estimate of the jammer signals. Analysis is needed to determine how much hardware error can be tolerated to obtain a desired level of jamming cancellation performance. We derive analytical, closed-form expressions that separately relate channel mismatch and phase noise to jamming cancellation ratio (CR) in a sidelobe cancellation system. We also validate our theoretical results using a high-fidelity simulation that models the phased array and signal processing chain, and obtain a close agreement between the theoretical and simulated results. By incorporating the errors in element- and subarray-level combining weights, we show that CR can be a misleading metric and it is more useful to consider the residue powers. We show that the residue power curve is proportional to the subarray pattern and provide design guidelines for improving jamming cancellation performance.

Time Sidelobe Correction of Hardware Errors in Stretch Processing

To obtain high-range resolution profiles of a target, stretch processing is often used when the required instantaneous bandwidth (sampling rate) is not available. Hardware errors introduce amplitude and phase distortions to radar signals that increase the time sidelobes (TSLs) of the dechirped returns. Calibration and digital correction of the transmitter and receiver hardware errors are required to obtain acceptably low TSLs. Prior work on calibration focused on providing conceptual frameworks without experimental detail. We implemented a complete TSL calibration procedure by modifying a technique from the literature and described the experimental setup that we used to study TSL behavior. We obtained an average TSL value of -55 dB for a waveform bandwidth of 512 MHz and instantaneous bandwidth of 15 MHz, when the same calibration data measurements were used in TSL correction. We also showed that TSL performance remained stable with an average TSL of -48 dB for 16 hr after calibration in a laboratory environment and with varying pulse lengths.

Hardware Limitations of Receiver Channel-Pair Cancellation Ratio

Interference cancellation techniques in multi-channel radar and communication systems, such as adaptive beamforming, are only effective if the response of each channel used is well matched. Though hardware variations between channels limit the intrinsic channel response match, digital equalization techniques improve channel-to-channel matching, as measured by the channel-pair cancellation ratio (CPCR). Digital receiver channel nonlinearities such as analog-to-digital converter (ADC) saturation and third-order nonlinearities, however, limit the level of channel matching achievable. We compare the effect of the use of linear frequency modulation (LFM) and band-limited Gaussian noise measurement (BLGN) signals on CPCR. We determine the impact of ADC saturation and analog-component third-order nonlinearities on each measurement signal through analysis, simulation, and experiments using a pair of S-band digital receivers. We show that the maximum achievable CPCR is lower for BLGN than LFM measurement signals due to ADC saturation and third-order nonlinearities.

IQ imbalance decorrelation in digital array radars

Digital array radars (DAR) with element-level digital transmission and reception present new opportunities for more advanced radar functionality and performance. In order to reduce RF front-end complexity while also reducing the need for high sample rates, the analog IQ demodulation receiver, or homodyne, is proposed so that only a single local oscillator (LO) is needed per element. An important homodyne receiver architecture impairment is IQ imbalance and its mitigation is the focus of this article. We introduce a new approach to IQ imbalance compensation, which leverages the digital array architecture to decorrelate these errors and significantly reduce their impact at the digital beam-formed output. As a result, we show that the image rejection ratio, defined as the ratio of the desired-signal power level to that of the image after digital beamforming is significantly higher than at any individual channel output. We derive a single compensation factor from the imbalance statistics estimated across all array elements. The compensation technique is then applied to measured data from a 32-element X-band homodyne DAR test bed.

A comparison of in-band linearity between element-digital arrays and active electronically-steered arrays

This work analyzes the differences in nonlinear performance between analog active electronically-steered and element-digital array architectures. The differences studied are based solely on receive array architecture. That is, the same low-noise amplifiers and receiver components were assumed in both architectures. The analysis demonstrates that for main-beam interferers the system third-order nonlinearity is worse for the analog architecture because its receive components after the beamformer are subjected to higher signal gain than in the digital array case. In the case of sidelobe interference, the analog beamformer acts as a spatial filter, reducing the power level coming into the nonlinear receiver proportionally to the sidelobe level. For sufficiently low sidelobe levels, the receiver nonlinear contribution is then smaller. However, for the highly-linear receiver chosen for this analysis, the element-digital architecture still maintains a linearity advantage. This allows a relaxation of the receiver linearity required in element-digital arrays to attain system-level linearity equal to that of the analog array. Coupled with an increasing level of integration, this linearity relaxation can balance the cost and power consumption associated with having a receiver in each array element, enabling the flexibility of element-level digitization.

An X-band element-level digital receive array

This paper describes the design and fabrication of an experimental 32-element receive digital array. The array is intended as a tool for researching digital array technologies and techniques. The paper describes the array architecture, the components chosen and the design of the RF and digital subsystems. Measured results are presented that show the effectiveness of our array calibration and error correction approach and demonstrate the scaling and improvement of the array-level signal-to-noise ratio over that of a single array element.