Salvador Pinillos Gimenez

Diamond layout style impact on SOI MOSFET in high temperature environment

This work performs an experimental comparative study between the Diamond (hexagonal gate geometry) and Standard layouts styles for Metal–Oxide–Semiconductor Field Effect Transistor in high temperatures environment. The devices were manufactured with the 1 lm Silicon-on-Insulator CMOS technology. The results demonstrate that the Diamond SOI MOSFET is capable to keep active the Longitudinal Corner Effect and the Parallel Association of MOSFET with Different Channel Lengths Effect in high temperature conditions and consequently to continue presenting a better electrical performance than the one found in the conventional SOI MOSFET.

Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices

This paper introduces a high-density layout style named overlapping circular-gate transistor (O-CGT) that allows the overlapping of circular gates from neighboring cells. With reference to rectangular-gate transistors (RGTs), higher aspect ratio per active area can be achieved. Besides, stray junction capacitances are minimal, improving switching performance. The first-order model for the O-CGT aspect ratio is used to size high-current devices of nominal on-resistance/current rate of 3.3 Ω/10 mA and 20 mΩ/2 A at V GS = 4.5 V. These power transistors were prototyped according to a standard mixed-signal 0.35-μm CMOS process and, respectively, occupy 1410 μm 2 and 0.541 mm2 , which represent an area saving of up to 60% as compared to RGTs of equivalent aspect ratio. Excellent fitting between O-CGT analytical and experimental data is attained. O-CGTs and RGTs exhibit very close IDS × VGS characteristics, with deviations limited to 0.8% and 5.36% on subthreshold and strong inversion regions, respectively. The O-CGT drain-source breakdown voltage is 8.91 V, slightly above RGT. The O-CGT topology represents then a good option in designing power stages in smart-power chips using planar fabrication processes.

Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET

This paper investigates and compares experimentally the total ionizing dose (TID) effects in digital parameters of the fully depleted (FD) OCTO Silicon-On-Insulator (SOI) n-type Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) (OSM), that presents an octagonal gate geometry, versus its conventional (rectangular gate geometry) counterpart (CSM). The main digital parameters taken into account in this study are the threshold voltage (VTH), subthreshold slope (SS), on-state drain current (ION) characteristics. This work demonstrates that OCTO layout style achieved higher radiation tolerance in terms of VTH and SS relative variation and keeping the higher ION performance, due to the LCE and PAMDLE effects existent in the OCTO layout style. In addition the OSM had a significant improvement in terms of the leakage drain current (ILEAK), whereas the CSM ILEAK performance was degraded.

An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs

This letter describes the impact of using a new gate geometry (ellipsoidal) rather than the standard one (rectangular) to implement planar metal-oxide-semiconductor field-effect transistors (MOSFETs). Our experimental results have been carried out using a 350-nm bulk complementary MOS technology node. We show that the proposed layout has been capable of increasing the ON-state and saturation drain currents in 2 and 3.2 times, respectively. In addition, the ellipsoidal MOSFET has been able to reduce the delay time constant by 61%. Therefore, we believe this new layout can be used as an alternative way to implement MOSFETs, boosting their analog electrical performance with an appropriate layout changing.

AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations

Analog integrated circuits (ICs) design is a complex task due to the large number of input variables that must be determined simultaneously in order to achieve different multiple design goals of an analog integrated circuit design, such as voltage gain (AV), unit voltage gain frequency (fT), slew-rate (SR), harmonic distortion (THD), etc. By using an evolutionary system based on Genetic Algorithm (AG) integrated to the SPICE simulator, named AGSPICE, this work aims to study, understand and calculate the different correlations between the MOSFETs inversion regimes and the design goals of an operational transconductance amplifier (OTA) operating in different design features. We believe that the AGSPICE can provide new design recommendations for the designers and reduce the design cycle time as well. Our experimental results with the AGSPICE are also compared to the results obtained manually and present compatible solutions to other works available in the related literature.

Comparative Experimental Study between Diamond and Conventional MOSFET

Diamond MOSFET (DM) layout (Fig. 1) was proposed in order to enhance the longitudinal electric field and consequently improve the average drift velocity in the channel ( ), the drain current (IDS) and the transconductance (gm) [1]. This innovative layout is based on gate hexagonal shape [1]. When applying the drain to source voltage (VDS), two components of longitudinal electric fields are generated, in contrast to the Conventional MOSFET (CM) that presents only one component [1]. The resultant (equivalent) longitudinal electric field in the channel of the DM is given by the vector sum of these two components of electric field that is higher than one found in the conventional counterpart [1].

Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment

An experimental comparative study of the high temperature effects between the diamond SOI MOSFET (DSM) and conventional SOI MOSFET (CSM) counterparts is performed. The Diamond layout style has demonstrated better electrical performance in high temperatures environment, mainly for high-frequency analog IC applications, regarding the same gate area, aspect ratio and bias conditions. This can be justified due to the longitudinal corner effect (LCE) and PAMDLE (parallel association of MOSFETS with different channel lengths) effects remain active in the diamond layout style at high temperature.

Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology

This paper studies the Early voltage behavior in circular gate partiallydepleted SOI nMOSFET. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Drain current comparisons with rectangular gate partiallydepleted SOI nMOSFET are performed, regarding the same effective channel length and width. Experimental results and three- dimensional simulations are used to qualify the results.

Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET

This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET birds beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.

Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs), named OCTO SOI MOSFETs (OSMs), in relation to the hexagonal [diamond SOI MOSFETs (DSMs)] and the standard (rectangular conventional SOI MOSFETs) ones regarding the same bias conditions. The devices were manufactured with a 1-μm fully depleted SOI complementary MOS (CMOS) technology. The main experimental findings demonstrate that OSM is capable of keeping active the longitudinal corner effect and the PArallel connection of MOSFET with Different channel Lengths Effect (PAMDLE) in its structure at high-temperature conditions, and consequently, it maintains its remarkably better electrical performance in comparison with the standard SOI MOSFET, mainly its capacity to reduce the leakage drain current, without causing any extra burden to the current planar SOI CMOS technology in relation to DSMs.