Samantha Lubaba Noor

Two-dimensional model of Dual Metal double gate tunnel FETs

Dual Metal double gate tunnel field-effect transistor (DMDG TFET) is a potential candidate for the next generation device fabrication. In this work a 2-D analytical model of the surface potential, electric field of DMDG TFET is developed by solving quasi-two-dimensional Poisson equation. These expressions can be numerically integrated to find the drain current. This model incorporates the effects of drain voltage, gate work function, gate length, gate dielectric thickness and silicon film thickness. The effectiveness of the proposed model is confirmed by a comparison with 2-D numerical simulations.

Threshold voltage sensitivity reduction of SOI four gate transistor

Threshold voltage of a SOI four gate transistor is studied to determine its dependency on different device parameters. A surface potential based analytical model is used for studying threshold voltage and an Atlas/Silvaco 3-D numerical model is also developed for the validation of the analytical model. The numerical model incorporates non-ideal effects like Shockley-Read-Hall recombination, concentration dependent mobility, Auger recombination and bandgap narrowing effect. Threshold voltage sensitivity on channel length variation is reduced by controlling device width (W) and silicon layer thickness (tsi). The idea is justified by both analytical model and numerical model.

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gausss law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

Triple material double gate TFET with optimized si film thickness

Triple material double gate (TMDG) tunnel field-effect transistor (TFET) can be considered as a potential nominee for next generation low power high speed device fabrication. In this study, the effect of Si film thickness on performance of TMDG TFET is analyzed using two dimensional TCAD simulations. The tunneling current is substantially dependent on device thickness and the device physics regulating it is outlined. Potential and electric field distributions along film thickness reveal that double gate pairing in TMDG TFET structure can lower the tunneling barrier width at the middle of the device until an optimized silicon film thickness is achieved and provide maximum drain current.

Simulation-based study on the effect of inversion charge layer on triple material double gate Tunnel FET

The impact of inversion charge layer on triple material double gate (TMDG) Tunnel FET (TFET) has been inspected in this work by using 2D TCAD simulations. Simulation results show that band-to-band tunneling current saturates due to inversion layer formation. Inversion charges cause the pinning of surface potential and make drain current less responsive to gate voltage. The contribution of source and drain in forming the inversion layer is measured quantitatively. The influence of different device parameters on inversion layer formation has also been inspected.

Impact of interface charges on the performance of Dual Material Double Gate tunnel FET

In this work, effect of interface charge on the performance of a Dual Material Double Gate (DMDG) Tunnel Field Effect Transistor (TFET) device has been studied. Due to the presence of high electric field in the device, interface charges are generated at oxide-semiconductor interface by hot carrier effect. A 2-D model of the device with interface charge has been developed in TCAD simulator and impact of both positive and negative interface charges has been observed in potential distribution, band profile, carrier concentration, tunneling current and threshold voltage. Since high electric field mainly exists in the source-body junction of the device, interface charges are mainly localized at that region. Effect of localized charge spreading over varying length has also been analyzed on surface potential and threshold voltage of the device. The study will be useful in fabrication and application of DMDG TFET devices.

Transient base charge modeling of IGBT and its carrier lifetime dependence

In many power converter applications, minority carrier lifetime assessment in the carrier storage region of IGBT is considered desirable. This paper presents a minority carrier lifetime estimation technique through investigation into transient base charge modeling of Non-punch Through (NPT) Insulated Gate Bipolar Transistor (IGBT). Parabolic approximation has been used for derivation of minority carrier concentration within the base. With the help of derived expression, an analytical model has been developed for transient base charge decay of IGBT in all minority carrier lifetime conditions. Better agreements with the experimental results have been found compared to the previously used linear model. Finally, the implications of carrier lifetime dependence on the charge decay rate are discussed, including implementation of such a carrier lifetime measurement technique.

Study of threshold voltage of p-channel four gate transistor

A three dimensional model of SOI p-channel four gate transistor has been developed using device simulator Silvaco/ATLAS. Threshold voltage for the device is studied for different biasing condition at the four gates and different physical parameter like channel length. The results are compared to the results obtained from the analytical model of threshold voltage of n-channel four gate transistor to find out whether the analytical model works for p-channel G4-FET also.

A comparative study of potential distribution of a thin film SOI p-channel four gate transistor

A comparative study of two different analytical models of accumulation-mode SOI p-channel G4-FET has been reported and accuracy of the models has been observed under different parametric variation and biasing conditions. A numerical model is developed by Silvaco/ATLAS 3-D simulator which incorporates various non ideal effects like concentration dependant mobility, Shockley-Read-Hall recombination, Auger recombination and bandgap narrowing effect. The accuracy of the analytical models are tested by the numerical model. The performance of varying different parameters like length, width, silicon thickness and gate biasing is also observed between lateral junction gates and between top and bottom gates.