Samar M. Ismail
German University in Cairo
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Publication
Featured researches published by Samar M. Ismail.
Circuits Systems and Signal Processing | 2016
Lobna A. Said; Samar M. Ismail; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu El-Yazeed; Ahmed M. Soliman
This paper presents three different optimization cases for normalized fractional order low-pass filters (LPFs) with numerical, circuit and experimental results. A multi-objective optimization technique is used for controlling some filter specifications, which are the transition bandwidth, the stop band frequency gain and the maximum allowable peak in the filter pass band. The extra degree of freedom provided by the fractional order parameter allows the full manipulation of the filter specifications to obtain the desired response required by any application. The proposed mathematical model is further applied to a case study of a practical second- generation current conveyor (CCII)-based fractional low-pass filter. Circuit simulations are performed for two different fractional order filters, with orders 1.6 and 3.6, with cutoff frequencies 200 and 500 Hz, respectively. Experimental results are also presented for LPF of 4.46 kHz cutoff frequency using a fabricated fractional capacitor of order 0.8, proving the validity of the proposed design approach.
international symposium on signal processing and information technology | 2007
Samar M. Ismail; Ali Ezzat Salama; Mohamed F. Abu-Elyazeed
In this paper, the hardware design and FPGA implementation of a new efficient three-dimensional wavelet transform (3D-WT) algorithm for video compression is presented. This algorithm performs the temporal decomposition of a video sequence in a more efficient way than the classical 3D-WT algorithm. It exhibits lower memory demands and lower latencies for the compression and decompression processes than the classical one. This makes the addressed algorithm fits better for real-time video processing. The hardware design is based on the use of the transposed-form FIR filter structure which is hereby compared to the direct-form FIR filter. The former is found to exhibit less clock latency and less chip area utilization. The reference design is made scalable to any wavelet filter coefficients and to fit for any frame size. The chip area utilization is compared upon the FPGA implementation at different frame sizes. The designed system can be used for real-time video applications.
2015 International Conference on Science and Technology (TICST) | 2015
Samar M. Ismail; Lobna A. Said; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu-Elyazeed; Ahmed M. Soliman
This paper presents a generalized form of the fractional logistic map. Two general parameters a and b are added to the classical fractional logistic equation. The effect of such parameters on the map is studied explicitly, in combination with the fractional order parameter α, which offers an extra degree of freedom increasing the design flexibility and adding more controllability on the design. The vertical and the zooming map are two special maps that arise as a result of the added parameters. Moreover, different design problems are offered in this work, as a resultant of the control of all these parameters at hand. This shows that any application specific map can be designed, highlighting the flexibility and integrity of the design. The combination of the added extra parameters a and b in addition to the system parameter ρ and the initial condition x0, as well as the fractional order parameter α makes the proposed generalized fractional logistic map the most favorable in constructing more efficient encryption keys.
Journal of Advanced Research | 2018
Samar M. Ismail; Lobna A. Said; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu-Elyazeed
Graphical abstract
international conference on modern circuits and systems technologies | 2017
Samar M. Ismail; Lobna A. Said; Ahmed A. Rezk; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu-Elyazeed; Ahmed M. Soliman
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the double humped logistic map as well as the fractional order logistic map. The mixing of the map parameters and the initial conditions x0, offers a great variety for constructing more efficient encryption keys. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE, NPCR as well as UACI measurements. The encryption system is proven to be highly sensitive to ±0.001% perturbation of the logistic maps parameters. The system is tested on medical images of knee MRI and a lung X-rays.
Archive | 2018
Wafaa S. Sayed; Samar M. Ismail; Lobna A. Said; Ahmed G. Radwan
Abstract Chaos theory describes the dynamical systems which exhibit unpredictable, yet deterministic, behavior. Chaotic systems have a remarkable importance in both modeling and information processing in many fields. Fractional calculus has also become a powerful tool in describing the dynamics of complex systems such as fractional order (FO) chaotic systems. The FO parameter adds extra degrees of freedom which increases the design flexibility and adds more control on the design. The extra parameters increase the chaotic range. This chapter provides a review of several generalized discrete time one-dimensional maps. The generalizations include a signed control parameter, scaling parameters, and shaping parameters. The properties of the generalized fractional logistic map are presented. The generalized fractional tent map is presented and its properties are studied and validated using numerical simulations. Various simulations are conducted including time series, bifurcation diagrams, and various chaotic properties against the system parameters and FO parameter.
international conference on modern circuits and systems technologies | 2017
Samar M. Ismail; Lobna A. Said; Ahmed A. Rezk; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu-Elyazeed; Ahmed M. Soliman
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the one dimensional double humped logistic map as well as the two-dimensional delayed logistic map. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE, NPCR as well as UACI measurements. The encryption system is proven to be highly sensitive to ±0.001% perturbation of the logistic maps parameters. The system is tested on medical images of palm print as well as Parkinson disease MRI images.
2015 International Conference on Science and Technology (TICST) | 2015
Samar M. Ismail; Lobna A. Said; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu-Elyazeed; Ahmed M. Soliman
This paper presents the generalization of a delayed version of the logistic map. The effect of the added two general parameters is studied, which offers the option of having three different maps. The dynamic behavior of the vertical, zooming and the general map is analyzed. The study of the fixed points, stability ranges and bifurcation diagram of the delayed logistic map at hand is detailed in this work. The flow of the system behavior from stability to chaos is also presented with its transient response as well as its phase plane portraits. Moreover, using the general parameters, the option of designing any specific map is validated by some design examples, which makes it more optimal for any specific applications. The added general parameters offer increased randomness with controllability of the map design, making it more suitable for pseudo-random sequence generators which are used in image encryption algorithms and in secure communication transfer.
international symposium on signal processing and information technology | 2008
Ahmad Anwar Abdellatif; Samar M. Ismail; Darek Korzec
In this paper, a field programmable gate array (FPGA) implementation of a Viterbi decoder using register exchange algorithm (REA) is presented. The REA offers a higher operating frequency than its competitor the trace back algorithm (TBA). The proposed design is compatible with the digital video broadcasting for terrestrial networks (DVB-T). The design uses less area and operates at a higher frequency than the existing designs. A multirate de-puncturing unit is integrated in the design to support five code rates of 1/2, 2/3, 3/4, 5/6, 7/8, which are adopted by the DVB-T standard.
Aeu-international Journal of Electronics and Communications | 2017
Samar M. Ismail; Lobna A. Said; Ahmed A. Rezk; Ahmed G. Radwan; Ahmed H. Madian; Mohamed F. Abu-Elyazeed; Ahmed M. Soliman