Sameer M. Bataineh

Closed form solutions for bus and tree networks of processors load sharing a divisible job

Optimal load allocation for load sharing a divisi ble job over processors interconnected in either a bus or a tree network is considered. The processors are either equipped with front-end processors or not so equipped. Closed form solutions for the minimum fin ish time and the optimal data allocation for each pro cessor are obtained. The performance of large sym metric tree networks is examined by aggregating the component links and processors into a single equiv alent processor. This allows an easy examination of large tree networks. In addition it becomes possible to find a closed form solution for the optimal amount of data that is to be assigned to each processor in the tree network in order to achieve the minimum finish time.

Bus-oriented load sharing for a network of sensor driven processors

A load-sharing problem involving the optimal allocation of measurement data among n sensor-driven processors interconnected through a bus-type communication medium is considered for three distinct architectural configurations. It is found that a minimal-time solution can be achieved if the computations by the processors end simultaneously. Simple recursions for the determination of the optimal allocation of load are presented. It is shown that for this problem a small number of processors can be almost as effective as a larger number. >

Power demand prediction using fuzzy logic

Abstract The paper discusses the implementation of a fuzzy-logic approach to provide a structural framework for the representation, manipulation and utilization of data and information concerning the prediction of power commitments. A neural network would then be implemented to accommodate and manipulate the large amount of sensor data involved. A training facility could allow the system to replace the requirement for skilled dispatchers in scheduling the generators. An algorithm has been implemented and trained to predict the total power demand on an hourly basis. The parameters taken into consideration cover environmental and weather-related conditions. Prediction of the power demand at each geographical load point, and hence the country-wide demand, has been tested in Jordan. Results concerning the daily prediction have been obtained. It is found to be very promising, especially in that the prediction is evaluated in a fuzzy environment.

Efficient scheduling algorithm for divisible and indivisible tasks in loosely coupled multiprocessor systems

In this paper, we investigate a scheduling problem in loosely coupled multiprocessor systems. This problem has been addressed by many researchers because it has a substantial effect on the performance of multiprocessor systems. Previous work considered only one class of tasks to be scheduled. In this paper, we propose an algorithm to schedule two classes of tasks, indivisible and divisible tasks, among the available processors in the system. The objective is to find the best scheduling that gives a minimum finish time. The divisible class of tasks, considered here for the first time in a scheduling algorithm, has important applications in signal-processing, image-processing and Kalman filtering. The proposed algorithm answered many important questions that arise when the two classes of divisible and indivisible tasks are considered. Applications of the algorithm include all operating systems with multiprocessor support, such as the Mach operating system. Although two classes of tasks are considered, the complexity of the algorithm stays in a reasonable order.

High Performance AES Design using Pipelining Structure over GF((2 4 ) 2 )

High data throughput AES hardware architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. The blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. Furthermore, the AES is internally evenly divided to ten pipeline stages; with the addition feature that the shift rows block (ShiftRow) is structured to operate before the byte substitute (ByteSubstitute) block. The use of this swapping operation has no effect on the AES encryption algorithm; however, it streamlines the process of four blocks of data in parallel rather than 16 blocks which is considered the key advantage for area saving. We evaluate the performance of our new implementation and current implementations in terms of throughput rate and hardware area for ALTERA MAX3000A family FPGA EMP3128ATC100-5. The simulation results show that the proposed AES has higher throughput rate of about 16% than the general AES pipeline structure with a saving hardware area of 36%.

Research: Effect of fault tolerance and communication delay on response time in a multiprocessor system with a bus topology

The effect of interprocessor communication and fault tolerance on the response time of N processors (nodes) interconnected through a bus type communication medium is discussed. Deterministic as well as probabilistic approaches are considered. Four correction methods to handle the unprocessed data by the faulty processor(s) are studied and compared. It is found that the effect of interprocessor communication and fault tolerance on the response time for communication-extensive programs (I/O bound) is more than that for computation-extensive programs (CPU bound). It is also found that the effect of fault tolerance on the response time is significant, and cannot be ignored when evaluating the performance of multiprocessor systems. We have shown that the work presented in this paper for a bus topology can be generalized and readily adopted by other multiprocessor network topologies.

Performance limits for processor networks with divisible jobs

Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a professor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.

CLEAR: A Cross-Layer Enhanced and Adaptive Routing Framework for Wireless Mesh Networks

Wireless Mesh Networks (WMNs) provide a new and promising solution for broadband Internet services. The distinguishing features and the wide range of WMNs’ applications have attracted both academic and industrial communities. Routing protocols play a crucial role in the functionality and the performance of WMNs due to their direct effect on network throughput, connectivity, supported Quality of Service (QoS) levels, etc. In this paper, a cross-layer based routing framework for multi-interface/multi-channel WMNs, called Cross-Layer Enhanced and Adaptive Routing (CLEAR), is proposed. This framework embodies optimal as well as heuristic solutions. The major component of CLEAR is a new bio-inspired routing protocol called Birds’ Migration Routing protocol (BMR). BMR adopts a newly developed routing metric called Multi-Level Routing metric (MLR) to efficiently utilize the advantages of both multi-radio/multi-channel WMNs and cross-layer design. We also provide an exact solution based on dynamic programming to solve the optimal routing problem in WMNs. Simulation results show that our framework outperforms other routing schemes in terms of network throughput, end-to-end delay, and interference reduction, in addition to being the closest one to the optimal solution.

Closed Form Solutions for Bus and Tree Networks of Processors Load Sharing A Divisible Job

Optimal load allocation for load sharing a divisi ble job over processors interconnected in either a bus or a tree network is considered. The processors are either equipped with front-end processors or not so equipped. Closed form solutions for the minimum fin ish time and the optimal data allocation for each pro cessor are obtained. The performance of large sym metric tree networks is examined by aggregating the component links and processors into a single equiv alent processor. This allows an easy examination of large tree networks. In addition it becomes possible to find a closed form solution for the optimal amount of data that is to be assigned to each processor in the tree network in order to achieve the minimum finish time.

Reliable Omega Interconnected Network for Large-Scale Multiprocessor Systems

The omega network has various attractive topological properties. It supports both one-to-one message routing and broadcast routing. Independent of the system size, every node in the network has a fixed size; therefore, it is used intensively in large-sized systems. In this paper, we examine a reliable omega-based multiprocessor system that preserves its full rigid omega configuration even in the presence of faults. The proposed omega interconnection network can tolerate any single and many multiple node failures, giving rise to significantly improved reliability. Reconfiguration in response to a single or multiple faults in the new design is easy and may be performed in a distributed manner. Unlike the reliable butterfly network, in the proposed reliable omega network, if a node at stage zero fails, the system will not lose a connection to one of its input/output ports. Reliability results show that our design compares favorably with an earlier one.