Sameer Shekhar

Analytical decomposition of power delivery network response for ramp loads

Minimizing power supply voltage noise is critical for high performance microprocessors. This paper uses time domain analysis to explore dependencies between design parameters, voltage response and impedance profile for ramp type loads that are common to compute logic blocks. It is shown that the conventional impedance profile based design is not sufficient. In addition the analysis clarifies non-intuitive behaviors of the voltage response, and leads to guidelines for design space exploration.

Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator Based Microprocessor Power Delivery

The focus of this paper is power integrity design for noise sensitive circuits in the context of integrated voltage regulators (IVRs). Analysis and design require a combination of traditional noise mitigation and power conversion techniques simultaneously accounting for distributed load, parasitics, and decoupling, and IVR control mechanisms. Both passive and active techniques are described to target noise components based on the electrical proximity to their source and the intervening IVR controls. Simulation results are used to illustrate the concepts and effectiveness of design options.

Novel Power Delivery Noise Mitigation Scheme Using Negatively Coupled Inductors

Noise coupling between different circuits powered by a single voltage regulator needs to be mitigated for functionality and performance targets like speed and jitter. This paper presents the idea of using negatively coupled inductors to suppress noise coupled between loads. Mathematical description of a simple two load case is used to illustrate efficacy and derive design guidelines. Circuit topologies with principles to generate minimal realizations for arbitrary number of loads are explained. Transient and frequency domain simulation results validate the theory presented showing up to 75% coupled noise mitigation and 30% overall noise reduction. Passive structures for realization on standard printed circuit board and substrate technology are included along with sample 3D-extraction results to establish their applicability.

Data interface buffer compensation scheme for fast calibration

Microprocessors and FPGAs need to enable simpler and compact platforms via integration of self-contained test and training circuits, training of data interface buffers for process and temperature variation being a prime example. This paper studies package embedding of resistors for buffer tuning and presents a scheme to utilize a single resistor to train a large number of buffers without increase in latency. Using SNR analysis, transient noise simulations and the consequent filtering latencies it is shown that embedding the compensation resistor on the package reduces the calibration time by 5µs while also reducing the filter size by a factor of 10.

Electrical modeling for sub-millivolt noise in compact IoT system designs

All IoT systems require multiple sensors to collect environment information via analog to digital convertor (ADC). In several medical applications and industrial instrumentation, signals need to be captured with high resolution therefore the ADC requires an extremely quiet reference. This paper presents modeling and physical design considerations for a 12-bit ADC reference voltage supply to meet a 244 μV noise target. A fully differential approach is used in the electromagnetic and circuit modeling to capture noise on all parts of the passive network. Noise quantification accuracy is studied for different analyses that are part of the design flow: FEA, macro-modeling & SPICE simulation. Noise reduction in physical design through PVT invariant band gap and electromagnetic isolation through Faraday cage are investigated.

Guard band reduction via dynamic voltage sensing and reference setting schemes in power gated applications

Use of power gates for leakage power reduction comes at the expense of higher DC and AC load lines due to location of voltage regulator sense point before the power gate and choice reference voltage to guarantee minimum voltage across all power gate and load conditions. This paper proposes schemes to dynamically change both the sense voltage and the reference voltage to reduce AC & DC load lines and consequently voltage guard bands. The simultaneous choice in sense and reference centers the load voltage variation between different gated domains providing an optimal solution without increase in maximum voltages. Application to client microprocessors show a benefit of a few tens of milli-Volts.

Interconnected capacitors for effective power delivery noise suppression across domains

Optimal power delivery network design relies on decoupling capacitors that consume significant package and board real estate, which is becoming scarce due to shrinking chip sizes and overall system form factors. This paper addresses noise reduction via capacitor interconnection between different voltage domains to leverage decoupling capacitors across domains. Novel structures that integrate decoupling and interconnection capacitor are then proposed. The complete solution delivers more than 40% noise reduction per unit capacitor area. Simulation results are provided for illustration.

Enhanced interconnects through filled metal structures

This paper analyses use of solid metal fill between BGA balls or LGA pins of packages, and between die bumps. The basic principle is to benefit from higher metal-density per unit volume of the substrate in the current path to deliver enhanced electrical, thermal and mechanical performance. Paper conceptualizes different structures and simulated data is presented to show case benefits. Results show power delivery impedance peak reduction by 10 % in the 100 kHz-10 MHz range. In addition, package inductor benefit of 40 % lower DC resistance is reported.

Performance and power implications of decoupling allocation with power gated domains

Gated power delivery network (PDN) system design requires careful decoupling capacitor allocation between ungated and gated loads. This paper illustrates the pros and cons of ungated and gated capacitors to system performance based on impedance and latency characterization. Solution with only ungated decoupling gives power benefits whereas gated decoupling provides optimized performance but larger latency. Simulations of microprocessor packages are used to illustrate challenges and decision factors.