Samuel H. Fuller

Cm*: a modular, multi-microprocessor

This paper describes the architecture of a new large multi-processor computer system being built at Carnegie-Mellon University. The system allows close cooperation between large numbers of inexpensive processors. All processors share access to a single virtual memory address space. There are no arbitrary limits on the number of processors, amount of memory or communication bandwidth in the system. Considerable support is provided for low level operating system primitives and inter-process communication.

Multi-microprocessors: An overview and working example

Rapid and continuing advances in large-scale integrated (LSI) semiconductor technology have lead to considerable speculation on ways to exploit microprocessors for building computer systems. Microprocessors are being applied very successfully where small amounts of computing power ate needed, such as in calculators, instruments, controllers, intelligent terminals, and more recently in consumer goods and games; but it remains an open problem to design a commerdally viable multiple-microprocessor structure. A variety of organizations have been proposed for such systems, and this article begins with an overview of this spectrum. Few multiple-microprocessor systems, however, have been built or otherwise subjected to a critical analysis. To address the unresolved problems facing such systems, Carnegie-Mellon University has undertaken the design, implementation, and evaluation of an experimental multi-microprocessor computer system called Cm*. A 10-processor, ½ Mbyte primary memory prototype configuration of Cm*has been completed and became available for experimentation in the Spring of 1977. The kernel of an operating system and five application programs with widely varying characteristics have been written for Cm*, and form the basis for the measurements and discussion given here. Several of the application programs have been able to utilize all the processors in the prototype system effectively. In other words, doubling the number of available processors effectively doubled the execution speed of these programs.

Performance of height-balanced trees

This paper presents the results of simulations that investigate the performance of height-balanced (HB[k]) trees. It is shown that the only statistic of HB[1] trees (AVL trees) that is a function of the size of the tree is the time to search for an item in the tree. For sufficiently large trees, the execution times of all procedures for maintaining HB[1] trees are independent of the size of the tree. In particular, an average of .465 restructures are required per insertion, with an average of 2.78 nodes revisited to restore the HB[1] property; an average of .214 restructures are required per deletion, with an average of 1.91 nodes revisited to restore the HB[1] property. Moreover, the execution times of procedures for maintaining HB[k] trees, for k > 1, are also independent of the size of the tree except for the average number of nodes revisited on a delete operation in order to restore the HB[k] property on traceback. The cost of maintaining HB[k] trees drops sharply as the allowable imbalance (k) increases. Both analytical and experimental results that show the cost of maintaining HB[k] trees as a function of k are discussed.

Measurement and Evaluation of Alternative Computer Architectures

The Army/Navy Computer Family Architecture Committee has developed an approach for quantifying the relative performance of alternative computer architectures.

An Analysis of Drum Storage Units

This article discusses the modeling and analysis of drum-like storage units. Two common forms of drum organizations and two common scheduling disciplines are considered: the file drum and the paging drum; first-in-first-out (FIFO) scheduling and shortest-latency-time-first (SLTF) scheduling. The modeling of the I/O requests to the drum is an important aspect of this analysis. Measurements are presented to indicate that it is realistic to model requests for records, or blocks of information to a file drum, as requests that have starting addresses uniformly distributed around the circumference of the drum and transfer times that are exponentially distributed with a mean of 1/2 to 1/3 of a drum revolution. The arrival of I/O requests is first assumed to be a Poisson process and then generalized to the case of a computer system with a finite degree of multiprogramming. An exact analysis of all the models except the SLTF file drum is presented; in this case the complexity of the drum organization has forced us to accept an approximate analysis. In order to examine the error introduced into the analysis of the SLTF file drum by our approximations, the results of the analytic models are compared to a simulation model of the SLTF file drum.

Computer Modules: An architecture for large digital modules

This paper describes the architecture of Computer Modules, or CMs. They are large digital modules of about minicomputer complexity that are specifically designed to take advantage of the rapidly advancing semiconductor technology. These modules are intended to be interconnected into systems that implement a wide range of computational structures. The main features of a CM include a small processor as the primary control element and memory distributed among the CMs in the system rather than centralized into memory modules as in current multiprocessors. CMs are interconnected into a network via buses that each have their own virtual address space to facilitate efficient inter-module memory sharing. This paper includes an ISP description of the address translation mechanisms as well as a discussion of several important implementation issues such as the avoidance of deadlocks in CM networks and the width of the inter-CM buses.

An Optimal Drum Scheduling Algorithm

Suppose a set of N records must be read or written from a drum, fixed-head disk, or similar storage unit of a computer system. The records vary in length and are arbitrarily located on the surface of the drum. The problem considered here is to find an algorithm that schedules the processing of these records with the minimal total amount of rotational latency (access time), taking into account the current position of the drum. This problem is a special case of the traveling salesman problem. The algorithm that is developed has the attractive property of exhibiting a computational complexity on the order of N log N.

Some Observations on Semiconductor Technology and the Architecture of Large Digital Modules

Modules for computer system design are becoming increasingly complex, driven by decreasing cost and size of hardware and increasing computer system performance requirements. Standard modules have evolved from circuit elements to gates and flip-flops to integrated-circuit chips to register-transfer level module sets. Because of the continuing development of semiconductor technology, LSI components — e.g., memory chips with ≥ 1K bits and microprocessors — may become the standard components of digital design. Are these memory arrays and microprocessors the right set of large modules to use in the next generation of digital system design? To discuss this and related questions, a workshop on the architecture and application of digital modules was held on June 7–8, 1973, at Carnegie-Mellon University. To ensure as wide a range of perspectives as possible, participants were invited from computer manufacturers, semiconductor manufacturers, and universities.

Markov chain models for analyzing memory interference in multiprocessor computer systems

This paper discusses various analytical techniques for studying the extent of memory interference in a multiprocessor system with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by an interval of processing time. The system is assumed to be bus bound; in other words, by the time the processor-memory bus completes servicing a processors request the processor is ready to initiate another request and the memory module is ready to accept another request. The techniques discussed include discrete and continuous time Markov chain models as well as several approximate analytic methods.

Price/performance comparison of C.mmp and the PDP-10

The analysis in this paper shows a multiprocessor like C.mmp to have a factor of three to four cost/performance advantage over uniprocessor systems such as the PDP-10 when implementations using similar technologies are considered. This comparison is shown to be very sensitive to memory prices and considerable attention is given to normalizing memory costs between C.mmp and the PDP-10. An important part of this analysis is a comparison of the PDP-10 architecture with the PDP-11 architecture (i.e. the architecture of the processors of C.mmp). When the limited address space of the PDP-11 is not a problem, we see that to a close approximation it takes the same number of PDP-11 instructions (average length 25 bits) as PDP-10 instructions (length 36 bits) to represent a program. While the comparison in this paper explicitly considers multiprocessor degradation factors such as memory interference, it does not address the problem of writing software systems capable of taking full advantage of the multiprocessor structures. The comparisons in this paper are primarily ofcused on comparing the hardware structures of uniprocessors and multiprocessors. Work is now in progress at CMU that is attempting to evaluate the effectiveness of both individual multiprocessor structures application programs and multiprogrammed systems operating on C.mmp.