Sanchai Harnsoongnoen

CONFINED-CHALCOGENIDE PHASE CHANGE MEMORY WITH THIN METAL INTERLAYER FOR LOW RESET CURRENT BY FINITE ELEMENT MODELING

This paper reports on the confined-chalcogenide phase change memory with thin metal interlayer (CCTMI) with the operating reset current of 0.6mA-30ns. This cell offers low reset current with simple architecture and fabrication. Thermal and heat flux distribution of both the normal-bottom-contact (NBC) and a proposed CCTMI PCM cells were carefully analyzed and simulated by two-dimensional finite element modeling. It is intriguingly found that the reset operation current of the CCTMI cell is 44% lower than that of the NBC. CCTMI has capability to solve an over-programming fail issue due to confined heat dissipation in active area.

Confined-chalcogenide phase-change memory with thin metal oxide interlayer for low reset current operation

A confined-chalcogenide phase-change memory (CC) with thin metal oxide interlayer (TMOI) aimed to lowering the reset current is proposed in this paper. This proposed structure offer a reduction of the reset current by 65%, 50% and 34.38% in comparison with a normal-bottom-contact (NBC) cell, CC cell and NBC with TMOI cell, respectively. The electrical and thermal characteristics were investigated by using finite element modeling based on electro-thermal physics. It is intriguingly found that the resent current of the proposed cell is significantly reduced by inserting a thin metal oxide (TiO2) film in the middle Ge2Sb2Te5 (GST) and in between GST and TiN heater. Furthermore, the melting shapes and effect of quench speed on the memory cell is also discussed. This implies the high-speed and low-power consumption CC with TMOI cell structure that can hold a promise as a future technology as memory devices.

Comparison of electromigration for lead-free solder joints of Cu vs. Ni UBM flip chip structure

Flip chip solder joints made with Cu and Ni underbump metallurgy (UBM) on the chip under current stressing were studied. The effects of material and various thicknesses (5, 10, 15, and 20 µm) of UBM on reliability were investigated. The solder material used was lead-free (Sn4.0Ag0.5Cu). Time to failure of both cases (Cu and Ni UBMs) was forecasted through the physical damage occurring at the bump under current stressing by using two-dimensional Finite Element Method (FEM). The simulation results conclude that thicker UBM can enhance electromigration reliability. Moreover, the comparison of the time to failure between Cu UBM structure with that of Ni UBM structure indicates that the time to failure of the flip chip solder joint with Cu UBM structure is approximately 5% longer than the case of Ni UBM structure due to the lowering current crowding effect at Cu UBM in the solder joint which is clearly shown in the simulations.

Comparison on the performance of the confined-chacogenide with thin metal interlayer and optimised lateral phase change memories

This work, for the first time, presents the performance comparison between the lately proposed vertical confined-chacogenide phase change memory with thin metal interlayer (CCTMI) and a newly proposed optimised lateral (LP) phase change random access memory structure with a 180nm feature size. High programming current has been a critical challenge to realize a high-density. Comparison of its performance aimed on the programming power during the reset state of both technologies was carefully analysed and simulated by 3-D Finite Element Method. The results revealed that the newly proposed LP cell with optimised structure can generate heat 52% more effective than that of CCTMI.

Three-dimensional numerical simulation of electrostatic discharge sensitivity for phase-change memories

The sensitivity to electrostatic discharge (ESD) events of the phase change memory was investigated by using a three-dimensional finite element modeling based on electro-thermal physics. Analytical storage elements were tested on µ-trench structure during three ESD models stress, HBM model, MM model, and CDM model. It was found that the phase-change memory cell is failure when All ESD model voltage stress lower than 5V. The phase change memory cell must then be considered as very sensitive class-0 devices for HBM model, class-M1 for MM model and class-C1 for CDM model.

OPTIMIZATION OF PHASE CHANGE MEMORY WITH THIN METAL INSERTED LAYER ON MATERIAL PROPERTIES

This works reports, for the first time, the thorough study and optimisation of Phase Change Memory (PCM) structure with thin metal inserted chalcogenide via electrical resistivity (ρ) using finite element modeling. PCM is one of the best candidates for next generation non-volatile memory. It has received much attention recently due to its fast write speed, non-destructive readout, superb scalability, and great compatibility with current silicon-based mass fabrication. The setback of PCM is a high reset current typically higher than 1mA based on 180nm lithography. To reduce the reset current and to solve the over-programming failure, PCM with thin metal inserted chalcogenide (bottom chalcogenide/metal inserted/top chalcogenide) structure has been proposed. Nevertheless, reports on optimisation of the electrical resistivity using the finite element method for this new PCM structure have never been published. This work aims to minimize the reset current of this PCM structure by optimizing the level of the electrical resistivity of the PCM profile using the finite element approach. This work clearly shows that PCM characteristics are strongly affected by the electrical resistivity. The 2-D simulation results reveal clearly that the best thermal transfer of and self-joule-heating at the bottom chalcogenide layer can be achieved under conditions; ρ_bottom chalcogenide > ρ_metal inserted > ρ_top chalcogenide More specifically, the optimized electrical resistivity of PCMTMI is attained with ρ_top chalcogenide: ρ_metal inserted: ρ_bottom chalcogenide ratio of 1:6:16 when ρ_top chalcogenide is 10-3 Ωm. In conclusion, high energy efficiency can be obtained with the reset current as low as 0.3mA and with high speed operation of less than 30ns.