Sandeep Oswal

Challenges and considerations of analog front-ends design for portable ultrasound systems

High performance portable ultrasound imaging system is demanded by a wide variety of point of care applications. Ultrasound system minimization and improvement have been proven in the past several years. One of the main driving forces for portable ultrasound system minimization and improvement is the advanced semiconductor technology. Besides, transducer technology is further enhancing system sensitivity and reducing system cost. Corresponding silicon processes were selected for achieving low power, low noise and compact size in ultrasound analog front-end (AFE) design. The combination of bipolar and CMOS processes achieves significant power, noise and size reduction, as well as superior CW performance. Key considerations of ultrasound analog front-end were discussed and analyzed. Standard test procedures were developed to assist the design.

A DSL customer-premise equipment modem SoC with extended reach/rate for broadband bridging and routing

A highly-integrated DSL modem for residential gateway applications is described. The chip integrates a C62x based DSL PHY, AFE, line driver and receiver, power management, and broadband controller subsystem. A 0.13/spl mu/m 5M CMOS process is used to implement the 2.3W chip. Supplies are 1.5V for digital and 3.3V for analog subsystems.

A 0.13/spl mu/m CMOS four-channel ADSL2+ analog front-end for CO applications with 75mW per channel

An analog-front-end design including the power-management circuits to achieve an SoC ADSL CPE modem solution is presented. The integrated AFE with less than 2nV//spl radic/Hz input referred noise, dynamically adaptive hybrid and combination of the analog and digital filtering provides a single-chip solution.

Analog front-end and power management integration on a 0.13 /spl mu/m CMOS ADSL SoC

This paper describes the analog and power management aspects of a single chip asymmetric digital subscriber line (ADSL) customer premises equipment (CPE) router. We address the system partitioning between analog and digital resulting in optimum system cost and performance for a .13 /spl mu/m CMOS process.