Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Sandeep Singh Gill is active.

Publication


Featured researches published by Sandeep Singh Gill.


ieee international conference on advanced management science | 2010

Notice of Retraction Indian currency exchange rate forecasting using neural networks

Sandeep Singh Gill; Amanjot Kaur Gill; Naveen Goel

Predicting currency exchange rate and handling enormous data with traditional time series analysis has proven to be difficult. An artificial neural network may be more suitable for the task because no assumption about a suitable mathematical model has to be made prior to forecasting and being a stochastic method it can reach the near optimum solution in relatively lesser time. Furthermore, a neural network has the ability to extract useful information from large sets of data, which is required for a satisfying description of a financial time series. This paper discusses the various conventional analysis methods and neural network methodology to forecast the currency exchange rate. The paper also provides the effects of various topological parameters on the accuracy and training time of neural networks. A topology of neural network is proposed for the prediction of Indian currency exchange rate.


The Journal of Engineering | 2016

Secure Trust Based Key Management Routing Framework for Wireless Sensor Networks

Jugminder Kaur; Sandeep Singh Gill; Balwinder Singh Dhaliwal

Security is always a major concern in wireless sensor networks (WSNs). Several trust based routing protocols are designed that play an important role in enhancing the performance of a wireless network. However they still have some disadvantages like limited energy resources, susceptibility to physical capture, and little protection against various attacks due to insecure wireless communication channels. This paper presents a secure trust based key management (STKF) routing framework that establishes a secure trustworthy route depending upon the present and past node to node interactions. This route is then updated by isolating the malicious or compromised nodes from the route, if any, and a dedicated link is created between every pair of nodes in the selected route with the help of “” composite random key predistribution scheme (RKPS) to ensure data delivery from source to destination. The performance of trust aware secure routing framework (TSRF) is compared with the proposed routing scheme. The results indicate that STKF provides an effective mechanism for finding out a secure route with better trustworthiness than TSRF which avoids the data dropping, thereby increasing the data delivery ratio. Also the distance required to reach the destination in the proposed protocol is less hence effectively utilizing the resources.


Active and Passive Electronic Components | 2017

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Satyam Shukla; Sandeep Singh Gill; Navneet Kaur; H. S. Jatana; Varun Nehru

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio ( ), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.


Machine Intelligence and Research Advancement (ICMIRA), 2013 International Conference on | 2013

Design and Implementation of Process Controller for Direct Digital Control on FPGA

Gurvinder Singh; Sandeep Singh Gill

In manufacturing processes it is invariably required to control certain process parameters to maintain a stipulated level of quality. Process control really means that all the parameters of the process are kept at their respective set values subject to permissible deviation from the set or reference value (i.e. within permissible tolerance). The process controller operates on the error signal using a particular control algorithm such as PI (proportional integral) or PD (proportional derivative) or PID (proportional integral derivative) and generates an actuating signal for the control element. This paper scrutinizes the various design methodologies with a focus on industrial process control system. Further a design of process controller for Direct Digital controller is realized to control multiple process parameters, which is then implemented on Xilinx FPGA (XC3S-500E). The approach mainly focuses on finding a off the shelf single solution for controlling multiple process parameters.


international conference on computational intelligence and computing research | 2012

Implementation of modified variable step size least mean square algorithm in LabVIEW

Rashpinder Kaur; Gurjinder Singh; Balwinder Singh Dhaliwal; Sandeep Singh Gill

This paper presents implementation of modified variable step size least mean square adaptive algorithm using adaptive filter toolkit of LabVIEW software. User interface is designed using LabVIEW to obtain learning curve for adaptive algorithm. Simulation results are presented to compare the performance of the modified algorithm with the standard least mean square algorithms, Kwongs variable step size algorithm and robust variable step size algorithm. The results show that modified algorithm has good speed of convergence over the existing algorithms.


vlsi design and test | 2016

Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA

Ankit Gaurav; Sandeep Singh Gill; Navneet Kaur; Munish Rattan

In this paper the electrical performance of triangular trigate bulk FinFET at 20 nm has been optimized using Artificial Neural Network (ANN) and Genetic Algorithm (GA). For training the ANN a set of 42 samples with two inputs and four outputs was created by 3D TCAD numerical simulator using Drift Diffusion approach with Density Gradient Quantum Corrections model. The optimal value of fin height (Hfin) and gate oxide thickness (Tox) was found using GA corresponding to which the short channel effects like drain induced barrier lowering (DIBL), subthreshold swing (SS) and off current (loFF) were minimum and on current (Ion) was maximum. The ANN and GA have been found to successfully predict and optimize the electrical performance of triangular TG FinFET for different device parameters like Hfin and Tox. After ANN and GA optimization Ion Hoff improved by 11.86 %, DIBL reduced by 32.35 % and off state leakage current reduced by 40.65% at expense of 33.41% reduction in the drive current.


asia pacific conference on postgraduate research in microelectronics and electronics | 2010

Swarm Intelligence based circuit partitioning

Sandeep Singh Gill; Rajeevan Chandel; Ashwani Kumar Chandel

This paper presents a swarm Intelligence based circuit partitioning technique using particle swarm optimization method. The circuit is divided into partitions and number of interconnections between them is minimized. The proposed method gives excellent results in solving the stochastic problem of circuit partitioning.


Journal of optical communications | 2017

Analysis of secured Optical Orthogonal Frequency Division Multiplexed System

Harsimranjit Singh Gill; Kamaljit Singh Bhatia; Sandeep Singh Gill

Abstract In this paper, security issues for optical orthogonal frequency division multiplexed (OFDM) systems are emphasized. The encryption has been done on the data of coded OFDM symbols using data encryption standard (DES) algorithm before transmitting through the fiber. The results obtained justify that the DES provides better security to the input data without further bandwidth requirement. The data is transmitted to a distance of 1,000 km in a single-mode fiber with 16-quadrature amplitude modulation. The peak-to-average power ratio and optical signal-to-noise ratio of secure coded OFDM signal is fairly better than the conventional OFDM signal.


IEEE\/OSA Journal of Optical Communications and Networking | 2017

A novel chaos-based encryption approach for future-generation passive optical networks using SHA-2

Harsimranjit Singh Gill; Sandeep Singh Gill; Kamaljit Singh Bhatia

A physical layer enhanced secure future generation passive optical network (PON) based on chaotic signal scrambling and the secure hash algorithm (SHA) is proposed and demonstrated. In this paper, the architecture of a wavelength-division multiplexed orthogonal frequency division multiplexing (OFDM) PON system based on a centralized light source using direct detection is analyzed. A logistic chaos map is employed here for the scrambling of OFDM symbols in the frequency and time domains. Before transmitting the signal over optical fiber, a message- digest of scrambled and descrambled OFDM signals is computed and compared at the optical line terminal and optical network unit, respectively, to verify the actual data recovered. For the downstream channel, a 10 Gbps 32 quadrature amplitude modulation OFDM signal is successfully transmitted over a distance of 50 km single-mode fiber within the limits of the peak-to-average-power value. The results show that the proposed scheme can protect the system from bad actors and eavesdroppers, while chaos encryption with SHA-2 provides a robust and promising secure strategy for future-generation PON systems.


ieee power india international conference | 2016

Electrical characteristics of 14nm SiC-3C channel SOI FinFET with dual-k spacer

Navneet Kaur; Munish Rattan; Sandeep Singh Gill

FinFETs have been the most promising replacement of MOSFETs for nanoscale era. Below 20nm, performance is highly degraded due to severe short channel effects (SCEs). In this paper, the electrical performance of SOI FinFET has been examined at 14nm gate length. Channel material used is SiC-3C because of its high carrier transport. Dual-k spacers are used in the underlap region between gate and source/drain. Density gradient quantum correction model has been used in simulations to include quantum mechanical (QM) effects in the nanoscale device. Also, dependence of high field effects on mobility has been taken into account. Input parameters like buried oxide thickness, fin height and fin thickness were varied to analyze their impact on output parameters i.e. on current (Ion), off current (Ioff), on/off ratio (Ion/Ioff) and Subthreshold Swing (SS). It was observed that highest Ion of 1.128e-05 is achieved for Hfin=24nm and Tfin=8nm, leakage current obtained is 5.629e-15 for Hfin=16nm and Tfin=4nm, on/off current is of the order of 1e08. Minimum SS is 62mV/dec for thin fins of designed SOI FinFET.

Collaboration


Dive into the Sandeep Singh Gill's collaboration.

Top Co-Authors

Avatar

Navneet Kaur

Punjab Technical University

View shared research outputs
Top Co-Authors

Avatar

Munish Rattan

Guru Nanak Dev Engineering College

View shared research outputs
Top Co-Authors

Avatar

Amanjot Kaur Gill

Guru Nanak Dev Engineering College

View shared research outputs
Top Co-Authors

Avatar

Balwinder Singh Dhaliwal

Guru Nanak Dev Engineering College

View shared research outputs
Top Co-Authors

Avatar

Kamaljit Singh Bhatia

Sri Guru Granth Sahib World University

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Satyam Shukla

Indian Institute of Technology Patna

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Amarjot Kaur

Guru Nanak Dev Engineering College

View shared research outputs
Top Co-Authors

Avatar

Ankit Gaurav

Guru Nanak Dev Engineering College

View shared research outputs
Researchain Logo
Decentralizing Knowledge