Sandip Kundu

Statistical Yield Modeling for Sub-wavelength Lithography

Photolithography is at the heart of semiconductor manufacturing process. To support continued scaling of transistors, lithographic resolution must continue to improve. At todays volume manufacturing process, a light source of 193 nm wavelength is used to print devices with 45 nm feature size. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used. While RET techniques allow printing of sub-wavelength features, the feature length itself becomes highly sensitive to process parameters, which in turn detracts from yield due to small perturbations in manufacturing parameters. Yield loss is a function of random variables such as depth-of-focus, exposure dose, lens aberration and resist thickness. The loss-of-yield is also a function of systematic components such as specific layout structure and out-of-band radiation from optical source. In this paper, we present a yield modeling technique for a given layout, based on a statistical model for process variability. The key issues addressed in this paper are (i) layout error modeling, (ii) avoidance of mask simulation for chip layouts, (iii) avoidance of full Monte-Carlo simulation for variational lithography modeling, (iv) building a methodology for yield estimation based on existing commercial tools. Results based on our approach show that yield sensitivity increases at smaller feature sizes.

Fast statistical timing analysis by probabilistic event propagation

We propose a new statistical timing analysis algorithm, which produces arrival-time random variables for all internal signals and primary outputs for cell-based designs with all cell delays modeled as random variables. Our algorithm propagates probabilistic timing events through the circuit and obtains final probabilistic events (distributions) at all nodes. The new algorithm is deterministic and flexible in controlling run time and accuracy. However, the algorithm has exponential time complexity for circuits with reconvergent fanouts. In order to solve this problem, we further propose a fast approximate algorithm. Experiments show that this approximate algorithm speeds up the statistical timing analysis by at least an order of magnitude and produces results with small errors when compared with Monte Carlo methods.

On the design of robust testable CMOS combinational logic circuits

The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable.<<ETX>>

Testing and reliable design of CMOS circuits

1. Introduction.- 1.1 What is Testing ?.- 1.2 Faults and Errors.- 1.3 Different Types of CMOS Circuits.- 1.3.1 Static CMOS Circuits.- 1.3.2 Dynamic CMOS Circuits.- 1.4 Gate-Level Model.- 1.5 Fault Models.- 1.5.1 Stuck-at Fault Model.- 1.5.2 Stuck-open Fault Model.- 1.5.3 Stuck-on Fault Model.- 1.5.4 Bridging Fault Model.- 1.5.5 Delay Fault Model.- References.- Problems.- 2. Test Invalidation.- 2.1 The Test Invalidation Problem.- 2.1.1 Test Invalidation due to Circuit Delays.- 2.1.2 Test Invalidation due to Charge Sharing.- 2.2 Robust Testability of Dynamic CMOS Circuits.- References.- Additional Reading.- Problems.- 3. Test Generation for Dynamic CMOS Circuits.- 3.1 Path Sensitization and D-Algorithm.- 3.2 Boolean Difference.- 3.3 Fault Collapsing.- 3.4 Redundancy in Circuits.- 3.5 Testing of Domino CMOS Circuits.- 3.5.1 Testing of Gates with Series-Parallel Network.- 3.5.2 Testing of Gates with Non-Series-Parallel Network.- 3.5.3 Testing of a General Circuit.- 3.5.4 Ordering of Test.- 3.6 Testing of CVS Circuits.- References.- Additional Reading.- Problems.- 4. Test Generation for Static CMOS Circuits.- 4.1 Non-Robust Test Generation.- 4.1.1 Test Generation from a Gate-Level Model.- 4.1.1.1 The Jain-Agrawal Method.- 4.1.1.2 The Reddy-Agrawal-Jain Method.- 4.1.1.3 The Chandramouli Method.- 4.1.2 Test Generation at the Switch Level.- 4.1.2.1 The Chiang-Vranesic Method.- 4.1.2.2 The Agrawal-Reddy Method.- 4.1.2.3 The Shih-Abraham Method.- 4.2 Robust Test Generation.- 4.2.1 The Reddy-Reddy-Agrawal Method.- 4.2.2 Some Issues in Robust Test Generation.- References.- Additional Reading.- Problems.- 5. Design for Robust Testability.- 5.1 Testable Designs Using Extra Inputs.- 5.1.1 The Reddy-Reddy-Kuhl Method.- 5.1.2 The Liu-McCluskey Method.- 5.2 Testable Designs Using Complex Gates.- 5.3 Testable Designs Using Parity Gates.- 5.4 Testable Designs Using Shannons Theorem.- 5.4.1 Path Delay Faults.- 5.4.2 Robustly Testable Design.- References.- Additional Reading.- Problems.- 6. Self-Checking Circuits.- 6.1 Concepts and Definitions.- 6.2 Error-Detecting Codes.- 6.2.1 Codes for Detecting All Unidirectional Errors.- 6.2.2 t-Unidirectional Error-Detecting Codes.- 6.2.3 t-Burst Unidirectional Error-Detecting Codes.- 6.3 Self-Checking Checkers.- 6.3.1 Static vs Dynamic CMOS Implementations.- 6.3.2 Two-Rail Checkers.- 6.3.3 Parity Checkers.- 6.3.4 m-out-of-n Checkers.- 6.3.5 Berger Checkers.- 6.3.6 Checkers for Borden, Bose-Lin, Bose and Blaum Codes.- 6.3.7 Embedded Checker Problem.- 6.4 Self-Checking Functional Circuits.- References.- Additional Reading.- Problems.- 7. Conclusions.- References.

On output response compression in the presence of unknown output values

A circuit may produce unknown output values during simulation of an input sequence due to an unknown initial state or due to the existence of tri-state elements. For circuits tested using BIST, unknown output values make it impossible to determine a single unique signature for the fault free circuit. To accommodate unknown output values in a BIST scheme, we describe a procedure for synthesizing a minimal logic block that replaces unknown output values by a known constant. The proposed procedure ensures that the BIST scheme will be able to detect all the faults detectable by the input sequence applied to the circuit while allowing a single unique signature to be obtained.

On diagnosis of faults in a scan-chain

Testing screens for good chips. However, when test fall out is high (low yield) it becomes necessary to diagnose faults so that the manufacturing process or physical design can be fixed to improve yield. Several scan based diagnostic schemes are used in industry. They work when the scan chain itself is fault free. This paper describes a diagnosis system that can diagnose faults in a scan chain.<<ETX>>

A modeling approach for addressing power supply switching noise related failures of integrated circuits

Power density of high-end microprocessors has been increasing by approximately 80% per technology generation, while the voltage is scaling by a factor of 0.8. This leads to 225% increase in current per unit area in successive generation of technologies. The cost of maintaining the same IR drop becomes too high. This leads to compromise in power delivery and power grid becomes a performance limiter. Traditional performance related test techniques with transition and path delay fault models focus on testing the logic but not the power delivery. In this paper we view power grid as performance limiter and develop a fault model to address the problem of vector generation for delay faults arising out of power delivery problems. A fault extraction methodology applied to a microprocessor design block is explained.

On modeling crosstalk faults

Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.

A small test generator for large designs

We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 bytes per gate. The low memory requirements and high performance have been achieved by working with a larger but simpler search space, by simplifying decision making and backtracking and by using only implication techniques that are fast and that require no preprocessing.

Diagnosing scan chain faults

Testing screens for good chips. However, when test fall out is high (low yield) it becomes necessary to diagnose faults so that the manufacturing process or physical design can be filed to improve yield. Several scan based diagnostic schemes are used in industry. They work when the scan chain itself is fault free. In this paper we describe a diagnosis system that can diagnose faults in a scan chain. >