Sang-Jung Ra

A study on PLC synchronization based on PLC preamble correlation for DOCSIS 3.1 Downstream

In this paper, we propose a PLC synchronization method based on the correlation of PLC Preamble subcarrier in DOCSIS 3.1 Downstream system. The proposed method aims to find out the starting point of PLC Preamble OFDM symbol and to present the reference point for the allocation of pilot pattern used for channel estimation. We showed the performance of the proposed method through the maximum value detection of PLC preamble correlation.

A novel channel estimation and equalization method for DOCSIS 3.1 Downstream

We propose a novel channel estimation and equalization method optimized for the scattered and the continuous pilot patterns of DOCSIS 3.1 Downstream system. The proposed method aims not only to compensate the multipath interferences and OFDM symbol timing offsets but also to minimize the complexity of hardware implementation. We showed the performance of the proposed method through 4096QAM constellation analysis after channel equalization.

A study on common phase rotation compensation for coaxial transmission systems in the HFC network

We present a study result for common phase rotation compensation based on DSP and FPGA for coaxial transmission system in the HFC network. Recently, most of internet networks have HFC configuration. For 10Gbps speed in the HFC network, coaxial networks should support 10Gbps. For this, DVB-C2, DOCSIS 3.1, EPoC are developed. Especially, DVB-C2 attracts attentions for 8K-UHDTV services. Considering DVB-C2 in 10Gbps transmission, the common phase rotation should be compensated efficiently. The presented study result is focused on the computation and the processing of common phase rotation.

Simulation results according to bit truncation in 4k-FFT algorithm

In this paper, we present an efficient design and implementation of FFT algorithm which is an important part of OFDM system. 4k-FFT algorithm is proposed and implemented in field programmable gate arrays (FPGAs). We measure the quantization error of FFT algorithm. Measured results show the maximum quantization error of 6.793259/5.662575 (real/imaginary value in 12 stage MSB truncation), 3.112945/2.627586 (real/imaginary value in 12 stage LSB truncation), 0.000756/0.000458 (real/imaginary value in 6 stage LSB/6 stage MSB truncation).

Design and implementation of 6/12MHz switchable QAM modulator based on DOCSIS 3.0

In this paper, we present an efficient design and implementation of downstream QAM modulator for Digital CATV transmission. The Digital CATV transmission system enables the cable operators to offer high-speed multimedia service for Digital CATV subscribers in HFC network. 6/12MHz switchable QAM modulator for Digital CATV transmission is proposed and implemented in field programmable gate arrays (FPGAs). The Modulator, which can be modulate switchable bandwidth (6 or 12 MHz), consists of FEC encoder, a post-forward error correction (FEC) and a digital to analog converter (DAC). We measure the spectrum of QAM modulator output. Measured results show the maximum transmitted error vector magnitude (EVM) of 0.62% (64-QAM/6MHz), 1.05% (64-QAM/12MHz) and 0.69% (256-QAM/6MHz), 1.12% (256-QAM/12MHz).

Performance measurement of high-efficient OFDM based transmission system in commercial HFC network

This paper describes the results of a field test of an OFDM-based transmission system that uses digital video broadcasting for a cable system and is implemented using field programmable gate arrays (FPGAs). For the field test, a 4096QAM, 4096 Fast Fourier Transform (FFT), 9/10 code rate of a low-density parity check (LDPC), and 6-MHz channel bandwidth were selected. To evaluate the practical performance of the implemented transmission system, a commercial MPEG Analyzer is used for the performance evaluation.

Study on the influences of fractional frequency offset on PLC synchronization in DOCSIS 3.1

In this paper, we present the simulation results of FFO(fractional frequency offset) influences on PLC preamble correlation based PLC synchronization in DOCSIS 3.1 Downstream. FFO makes inter-carrier interferences and breaks orthogonality in OFDM based transmission system. It degrades the performance of OFDM by reducing SNR(signal to noise ratio). The performance of PLC synchronization is influenced by the reduced SNR caused by FFO. We analyzed the influences of FFO on PLC synchronization by applying various FFO values. We showed the PLC synchronization performances to various FFO values and discussed the results considering requirements of FFO compensation performance in OFDM signal reception.

Implementation and performance analysis of QAM modulator applicable to the HFC network

In this paper, we present an analysis of implemented QAM modulator in HFC network. It may be through the 256 QAM modulation using a single carrier to transmit data up to 38.8 Mbps. 64/256-QaM modulator based on ITU-T J.83 Annex B is implemented as a board which includes field programmable gate arrays (FPGAs). Implemented Modulator consists of RS-TCM encoder, a QAM modulator and Digital to analog converter (DAC). We analyze the received MPEG-2 TS stream and measured Program Clock Reference (PCR) jitter. TS stream is normally being received, PCR was confirmed to operate reliably within approximately -50 to +300 ns.

Measurement results of timing recovery in an implemented DVB-C2 system

A timing recovery is required to cope with the difference between a transmitter and receiver clock for a non-synchronous system. We have implemented and tested the timing recovery in a DVB-C2 system which uses an OFDM. We have measured the timing error detector, the loop filter output in the timing recovery and the uncoded-BER for 4096QAM whether the transmitter and receiver clock are the same or not.

Quantization Error According to Bit Truncation Method in 4k-FFT Algorithm

In this paper, we compare a quantization error performance of FFT algorithm according to bit truncation method. 4k-FFT algorithm of OFDM is proposed and implemented in field programmable gate arrays (FPGAs). We analyze the quantization error performance according to bit truncation method. Measured results show the maximum quantization error of 6.042152/6.067595 (real/imaginary value in 12 stage MSB truncation), 3.112953/2.627594 (real/imaginary value in 12 stage LSB truncation), 0.006065/0.005448 (real/imaginary value in 6 stage LSB/6 stage MSB truncation) in 1st method. And measured results show the maximum quantization error of 0.001464/0.00129 (real/imaginary value in truncation after FFT) in 2nd method.