Sang-Mo Koo

Ferroelectric Pb(Zr0.52Ti0.48)/SiC field-effect transistor

Nonvolatile operation of ferroelectric gate field-effect transistors in silicon carbide (SiC) is demonstrated. Depletion mode transistors have been realized by forming a Pb(Zr0.52Ti0.48)O-3/Al2O3 g ...

Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0u2009V and Vdd with a high voltage gain of ∼29 and a sharp transition of 0.28u2009V at Vddu2009=u20093u2009V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for Vdd = 3u2009V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits.

Ferroelectric Pb(Zr,Ti)O3/Al2O3/4H–SiC diode structures

Pb(Zr,Ti)O3 (PZT) films (450 nm thick) were grown on 4H–silicon carbide (SiC) substrates by a pulsed-laser deposition technique. X-ray diffraction confirms single PZT phase without a preferred orientation. Stable capacitance–voltage (C–V) loops with low conductance (<0.1u2009mS/cm2, tanu200aδ∼0.0007 at 400 kHz) and memory window as wide as 10 V were obtained when 5-nm-thick Al2O3 was used as a high band gap (Eg∼9u2009eV) barrier buffer layer between PZT (Eg∼3.5u2009eV) and SiC (Eg∼3.2u2009eV). High-frequency (400 kHz) C–V characteristics revealed clear accumulation, and depletion behavior. Although the charge injection from SiC is the dominant mechanism for C–V hysteresis in PZT/Al2O3/SiC, negligible sweep rate dependence and negligible applied bias dependence were observed compared to that of PZT/SiC. By using room-temperature photoilluminated C–V measurements, the interface states as well as the charge trapping in the PZT/Al2O3 stacks have been calculated.

Electrical characteristics of metal-oxide-semiconductor capacitors on plasma etch-damaged silicon carbide

Abstract The characteristics of metal-oxide-semiconductor (MOS) capacitors formed on inductively coupled plasma (ICP) etch-damaged SiC have been investigated. MOS capacitors were prepared by dry-oxidation on ICP-etch-damaged n- and p-type, 6H- and 4H-SiC. The effect of a sacrificial oxidation treatment on the damaged surfaces has also been examined. Capacitance–voltage and current–voltage measurements of these capacitors were performed and referenced to those of simultaneously prepared control samples without etch damage. The effective interface densities (NIT) and fixed oxide charges (QF) of etch-damaged samples have been found to increase while the breakdown field strength (EBD) of the oxide decreases. The barrier height (φb) at the SiC–SiO2 interface, determined from a Fowler–Nordheim analysis, decreased for MOS capacitors on etch-damaged surfaces. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged SiC.

SiC device technology for high voltage and RF power applications

Recently, silicon carbide (SiC) has drawn considerable attention as a suitable semiconductor material for high power, high frequency, high temperature and radiation resistant devices. The commercialized substrates and the experimental device prototypes in SiC show the promises while the continued improvements in fabrication techniques are required for economically viable productions to be widespread. This paper reviews the progress and current issues in SiC device process technology and the state-of-the art SiC devices for high voltage and RF power applications.

Processing and properties of ferroelectric Pb(Zr,Ti)O-3/silicon carbide field-effect transistor

Metal-ferroelectric-(insulator)-semiconductor MF(I)S structures have been fabricated and the properties of pulsed laser-deposited PZT/Al2O3 gate stacks have been studied on n- and p-type 4H-SiC. Among several polytypes of SiC, 4H-SiC is considered as the most attractive one because of its wider bandgap (E g ≅ 3.2 eV) as well as higher and more isotropic bulk mobility than other polytypes. Single PZT phase without a preferred orientation was confirmed by x-ray diffraction. The interface trap densities N IT, fixed oxide charges Q F, and trapped oxide charges Q HY have been estimated by C-V curves with and without photo-illuminated measurements at room temperature. It is found that the charge injection from SiC is the dominant mechanism for C-V hysteresis. Importantly, with PZT/Al2O3 gate stacks, superior C-V characteristics with negligible sweep rate dependence and negligible time dependence under the applied bias were obtained compared to PZT directly deposited on SiC. The MFIS structures exhibited very stable capacitance-voltage C-V loops with low conductance (<0.1 mS/cm2, tan δ ∼ 0.0007 at 400 kHz) and memory window as wide as 10 V, when 5 nm-thick Al2O3 was used as a high bandgap (E g ∼ 9 eV) barrier buffer layer between PZT (E g ∼ 3.5 eV) and SiC (E g ∼ 3.2 eV). The structures have shown excellent electrical properties promising for the gate stacks as the SiC field-effect transistors (FETs). Depletion mode transistors were prepared by forming a Pb(Zr0.52Ti0.48)O3/Al2O3 gate stack on 4H-SiC. Based on this structure, ferroelectric Pb(Zr,Ti)O3 (PZT) thin films have been integrated on 4H-silicon carbide (SiC) in a SiC field-effect transistor process. Nonvolatile operation of ferroelectric-gate field-effect transistors in silicon carbide (SiC) is demonstrated.

Recent advances and issues in SiC process and device technologies

Silicon carbide (SiC) is a wide band-gap semiconductor material with potential applications for high power, high frequency, and high temperature devices. Commercially available substrates and devices together with the shown experimental prototypes show very good promises for the future while still a continued improvement in fabrication techniques and wafer substrates are required for economically viable production. The recent advances and critical issues in SiC device process technology and the current state-of-the art devices in SiC are reviewed.

Effect of annealing temperature on the barrier height of nano-particle embedded Ni-contacts to 4H-SiC

In order to realize stable SiC (Silicon carbide) devices, metal contacts to SiC with suitable physical and electrical characteristics are required. For example, Ohmic contacts with low specific contact resistances and Schottky contacts with controlled barrier height (ΦB) between SiC and metal are among the most important factors for determining the performance of SiC devices. To date, extensive studies have been carried out on the properties of barrier height of various metals on n- and p-type for SiC and many attempts have been made to modify the contact barrier height on SiC depending on the annealing temperature. To change effectively lower the barrier height of the metal/SiC structures, it was required to anneal the contact formed on highly doped 4H-SiC substrates (>1018 cm−3) at high temperatures (900∼1000 °C) [1]. Recently, the electrical contacts to SiC includes the implementation of nanostructures such as metal nano-partices (NPs) to modify the barrier height at metal-SiC interfaces and to alter fundamental SiC device properties by controlling the size of the metal NPs [2]. Previous results in the literature have been primarily focused on the effect of size reduction of NPs on the characteristics of diode structures with embedded NPs, which experimentally investigates the change in transport properties of metal/semiconductor interfaces in SiC depending on the size of NPs. However, so far the focus has been mainly on the scaling effect of NPs rather than on altering the electrical barrier of the NPs [3].

Multifunction integration of junction-MOSFETs and nonvolatile FETs on a single 4H-SiC substrate for 300/spl deg/C operation

A novel integration of junction-MOSFETs (JMOSFETs) and nonvolatile FETs (NVFETs) on a single 4H-SiC substrate is presented. The SiC JMOSFET controls the drain current effectively from the buried junction gate, thereby allowing for a constant current level at elevated temperatures. The SiC NVFET has similar functions with nonvolatile memory capability due to its ferroelectric gate stack. This work is the first report on the integration of fully functional SiC JMOSFETs and NVFETs on the same substrate up to 300/spl deg/C.

Titanium-oxide based Nanoscale and Embeddable Subzero Temperature Sensor using MIT Deformation Characteristics

In this research, we propose a nanoscale and embeddable subzero temperature sensor that is made with a temperature-dependent titanium-oxide based metal-insulator-transition (MIT) device. For a nanoscale two-terminal structured MIT device, the MIT devices characteristics are noticeably changed from abrupt to gradual MIT under zero temperature, which is called MIT deformation. On the basis of the MIT deformation characteristics, subzero temperatures can be detected by reading current levels as temperature changes. Furthermore, this sensor has desirable sensing properties such as high-linearity and proper sensitivity. The obtained results strongly show that titanium-oxides with CMOS process compatibility, cost-effectiveness, nontoxicity, etc, can be applied at the nanoscale and embeddable on subzero temperature sensors on a chip.