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Dive into the research topics where Sang-Woong Yoon is active.

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Featured researches published by Sang-Woong Yoon.


radio and wireless symposium | 2009

A 34% tuning range CMOS VCO with linear frequency tuning

Kwang-Hoe Koo; Sang-Woong Yoon; Chang-Woo Kim

A CMOS voltage controlled oscillator(VCO) with additional parallel resistors in its LC resonator has been proposed to improve the tuning (frequency-to-voltage) linearity and reduce the tuning sensitivity KVCO. The VCO is linearly tunable from 806 to 1,113 MHz with a 34% tuning range controlled linearly by the tuning voltage. The phase noise of the VCO is −100.4 dBc/Hz at 100-kHz offset frequency from 903MHz carrier. The supply voltage was 1.8V with the current of 2.5 mA flowing through the differential core. The chip size is 0.815 × 0.680 mm2, which has been fabricated in a standard 180-nm CMOS technology.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2015

Efficient Wi-Fi Power Amplifier LTCC Module Using a Buck Converter With a Power Inductor Implemented in Ferrite-Filled PCB Technology

Sang-Woong Yoon; Trung-Sinh Dang; Ngoc-Duy-Hien Lai; Jae Y. Park

This paper presents a power amplifier module (PAM) that operates efficiently in low-power mode for IEEE 802.11g Wi-Fi applications. The PAM consists of a power amplifier (PA), a buck converter, and a power detector. Two packaging technologies were used to integrate the compact module: a low-temperature co-fired ceramic (LTCC) technology and a ferrite-filled printed circuit board (PCB) technology. The LTCC portion includes radio-frequency inductors, capacitors, transmission lines, and interconnection lines to minimize the overall size, while a power inductor for the buck converter is implemented in ferrite-filled PCB. The PA and the buck converter are designed in 2-μm InGaP/GaAs heterojunction bipolar transistor technology and 0.35-μm CMOS technology, respectively. The output power level is converted into a voltage by the power detector, and the voltage controls the buck converter, thereby optimizing the supply voltage of the PA. This adaptive supply voltage helps to improve the power-added efficiency (PAE) in the low-power regime while maintaining linearity. The PAM showed an error vector magnitude of less than 4% up to an output power of 22 dBm. The PAE is 8% and 11% at output powers of 11 and 16 dBm, respectively, representing respective improvements of 60% and 43%. The overall size of the PAM is 5×7.5×1.2 mm3.


asia pacific microwave conference | 2013

InGaP/GaAs WLAN power amplifier with detector using on-chip coupler

Trung-Sinh Dang; Anh-Dung Tran; Sun-Jun Ham; Hyun Woo Park; Lai-Ngoc-Duy Hien; Sang-Woong Yoon

This paper presents a power amplifier with an on-chip power detector for 2.4 GHz wireless local area network (WLAN) application. The power detector consists of a clamp circuit, a diode detector and a coupled line directional coupler. A series inductor for an output matching network in the power amplifier is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from 2 metamaterial units along the coupled line.


IEEE Microwave and Wireless Components Letters | 2016

A Wideband Active Phase Shifter using Positive and Negative Inductance/Capacitance

Ngoc-Duy-Hien Lai; Hyoungsoo Kim; Sang-Woong Yoon

This letter presents an active phase shifter providing a quasi-constant transmission (S21) phase over a wide frequency range. The active phase shifter consists of positive and negative inductance/capacitance(L/C). The transmission phase of the positive L/C is compensated by that of the negative L/C along the frequency. The active phase shifter was implemented in IBM 7RF 180 nm CMOS technology. The measured transmission phase ranged between -70° and -110° with a minimum phase variation of 10°, and the insertion loss ranged between 4 and 6 dB from 1.2 to 2.8 GHz. The size of the core chip was 650 × 800 μm2 .


Journal of Semiconductor Technology and Science | 2015

An Wideband GaN Low Noise Amplifier in a 3×3 mm2Quad Flat Non-leaded Package

Hyun Woo Park; Sun-Jun Ham; Ngoc-Duy-Hien Lai; Nam-Yoon Kim; Chang-Woo Kim; Sang-Woong Yoon

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a 0.25 μm GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the 3×3-mm 2 QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses (S11 and S22) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is 1.1×0.9 mm 2 . To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.


international soc design conference | 2010

DC-DC converter for WLAN power amplifier

Trung Sinh Dang; Anh Dung Tran; Min-Young Cho; Sang-Woong Yoon

A buck converter to control the supply voltage and a Power Amplifier (PA) for the Wireless Local Area Network (WLAN) application are presented in this paper. By using the buck converter the efficiency improvement in low power mode of the PA can be achieved. The buck converter is implemented in TSMC 0.35 μm CMOS process. The maximum efficiency of 98% is shown at 3.4 V of the output voltage of the buck converter, and the efficiency of 90% is achieved for 2 V with the load resistance of 12 Ω. The maximum ripple across the overall output voltage range is less than 12 mV. The WLAN PA is implemented in WIN 2 μm InGaP HBT process. The maximum linear output power of 22 dBm is obtained for the Error Vector Magnitude (EVM) of 4% with 64QAM OFDM signal at 2.5 GHz. The Power Added Efficiency (PAE) is 20% at 22 dBm.


IEEE Transactions on Components and Packaging Technologies | 2009

A Quality-Improved Folded Inductor Embedded in MCM-L Organic Packaging Substrate Using an Unfilled Via Process

Sang-Woong Yoon; Joy Laskar

This paper presents a folded inductor implemented with a multichip module, which involves a laminate organic packaging technology with an unfilled via process. The folded inductor had an increased inductor layer surface area because of the unfilled vias along the inductor layer. Thus, the quality (Q) factor of the inductor improved as the series resistance, resulting from the skin effect, decreased. The Q-factor for a folded inductor showed a maximum improvement of 32% by including contact resistances, in comparison with the Q -factors of a normal planar inductor.


Electronics Letters | 2014

Ultra-wideband power divider using three parallel-coupled lines and one shunt stub

Trung-Sinh Dang; Chang-Woo Kim; Sang-Woong Yoon


Electronics Letters | 2010

Fully-integrated wideband CMOS VCO with improved f – V linearity and low tuning sensitivity

Chang-Woo Kim; K.-H. Koo; Sang-Woong Yoon


Electronics Letters | 2010

Linearity enhanced 2.4 GHz WLAN HBT power amplifier using digitally-controlled tunable output matching network with pHEMT switch in GaAs BiFET technology

Sang-Woong Yoon; Seong-Lyun Kim

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Hyoungsoo Kim

University of North Texas

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