Sangeeta M. Joshi

Using FPGA-SoC interface for low cost IoT based image processing

Multifunction image processing systems are typically deployed at the application site, but with the advent of Internet of Things(IoT) the design of such systems that are accessible remotely by applications over the internet is the need of the hour. These systems, being designed for data heavy applications need to possess a novel architecture design for image filtering and processing. This paper presents a multifunction image processing system that is accessible over the internet and is prototyped using a System on Chip (SoC) and FPGA interface. A pipelined based approach, inspired by a shift register based Random Access Memory design has been implemented for on-the-fly computation and minimal use of on-chip resources. The realization of the system was done using a low cost Spartan 6 FPGA and a Raspberry-pi B+ representing the ARM cortex based SoC. Data transfer between the FPGA and SoC has been achieved using a UART protocol. Computation time of different frame sizes for the system and standard I.P. software tools have been documented. Chip utilization and delays have also been reported.

Efficient battery management in wireless sensor node: Review paper

Wireless sensor network is an emerging field in wireless networking. Wireless Sensor Node (WSN) is the key component of wireless sensor networks for data communication inn large networks. WSN is powered with battery as its source of energy. It is usually deployed in hostile. Alkaline batteries are dominantly used in WSN. We need to maximize utilization of battery used in WSN. In this paper we have reviewed various models of the alkaline battery for maximizing its utilization and its lifetime. A brief experiment on relaxation model has been carried out which is most suitable battery model for predicting lifetime of battery in WSN.

Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire)

This paper proposes a cylindrical vertical Gate-All-Around Transistor with nanowire of compound III-V semiconductor material In0.53Ga0.47As n-type device with channel length of 10 nm. The effect of variation of channel diameter and spacer length on the performance of the device is simulated. The device gives an acceptable Subthreshold Slope and Drain Induced Barrier Lowering along with satisfactory ION/IOFF ratio. The device is simulated in Sentaurus Synopsys using Hydrodynamic model for III-V semiconductors with Poisson equation to give the transfer characteristics.

Performance Evaluation of Improved Directional Ad Hoc on Demand Distance Vector Routing Protocol

Mobile ad hoc networks (MANET’s) popularly uses ad hoc on-demand distance vector (AODV) routing protocol. Past research has identified certain limitations on performance on AODV. This work discusses the results of a new protocol, improved directional AODV (ID-AODV) routing protocol; that has succeeded in improving the performance of MANET’s for energy, delay, packet delivery ratio and overheads as compared with networks using AODV. In ID-AODV, improvements are carried out in both network layer, and data link layer. The directionality is introduced based on hop count of its position from the source. The dual sensing directional media access control protocol is used to eliminate the hidden terminal, exposed terminal, and deafness issue. Participation of nodes in forming route is decided by checking remaining energy level of the node and also checking its load. A modified algorithm is used to reduce the delay. This algorithm reduces the delay by changing the time to live, wait time, and using expanded ring search technique. The simulation results show that the ID-AODV offers improved performance on average Energy consumption in the range of 17–20%, average end to end delay is lower by 61 to 95%, Overheads improved in the range of 10–13%, Jitter 6–21%, link break 43–52%, packet delivery ratio is 6–21% lower as compared to MANETS deploying AODV.

Performance enhancement and supression of short channel effects of 14nm double gate FETs by using gate stacked high-k dielectrics & workfunction variation

Double-gate (DG) MOSFETs became popular due to its excellent scalability and better immunity to short Channel Effects. They are used for CMOS applications beyond the 70 nm node of the ITRS roadmap. However DG devices with channel lengths below 100nm show considerable leakage current and threshold voltage roll off. In this paper, we propose and validate a novel design for a double-gate field-effect transistor (DG FET) with 14nm gate length. Impact of high-k dielectrics along with and without gate stacking with 0.5nm EOT and work function variation on Short Channel Effects (SCEs) is studied using visual TCAD 2-D. Effect of Variation of interfacial thickness layer in gate stack on SCEs is also observed. Tradeoff between threshold voltage and SCEs is observed in work function analysis. Improvement in SCEs is observed with work function optimization. Ion/Ioff ratio is observed for different work function values. Finally, optimized range for work function values is discussed for better suppression of SCEs.

Development of radio frequency energy harvesting module

Energy harvesting is the need of the hour to operate small, portable and low power electronic devices for self-reliance. We focus our research on radio frequency energy harvesting. We have designed micro strip patch antenna to operate at 2.4GHz. We have analyzed the capture of ambient radio frequency energy at various physical locations. We have successfully demonstrated the RF energy harvesting technique proposed for operating devices like LED, scientific calculator and battery charging. In this paper we have verified the RF energy harvesting technique through simulation and experiments.

Novel gate-all around triangular channel horizontal nanowire field-effect transistor for low power memories

This paper proposes a novel gate-all around (GAA) triangular channel horizontal nanowire field-effect transistor (HNWFET) for future low power memories. As the cross-sectional dimensions of nanowire channel are very small, an enhanced electrostatic controllability and carrier mobility characteristics are achieved. Ion, Ioff and the ratio Ion/Ioff have been chosen as the figure of merit to optimize the triangular channel HNWFET considering the parameters such as channel length, channel doping and temperature. The subthreshold slope (SS), Drain Induced Barrier Lowering (DIBL) and other device performance parameters are observed for optimized channel length using three-dimensional technology computer-aided design (TCAD). Our results show that reduction in channel length yields better ON-state and OFF-state characteristics with Ion as high as 0.0284mA and Ioff as low as 0.24pA.

A novel window function approach for voltage controlled memristor

Memristor being a fourth fundamental passive electrical circuit element in nanoscale technology has gained a great interest in the new era of semiconductor technology. The memristor with its special property of nonvolatility, low power consumption, small size and improved scalability has captured interest in many applications from digital logic circuits to neuromorphic computing. This paper will discuss and compare the most noteworthy models of voltage controlled memristor. We propose implementation of different window functions which can be implemented in the future voltage controlled memristor models to observe nonlinear hysteresis behaviour of memristor.

Empirical analysis and performance evaluation of a generic re-linking technique for robust route maintenance

Establishing and maintaining a route is a challenge in the design of resource constrained Wireless Sensor Networks. The paper investigates and evaluates a robust generic re-linking technique that aims to enhance route maintenance. Although the use of node residual energy has been exploited in routing protocols, the re-linking techniques for route maintenance need to be researched further. We opine that if data can be re-linked prior to the termination of an existing route on the onset of death of a node, data and energy loss can be reduced. The re-linking technique is fast in response and ensures minimal route disturbance. This eliminates the need to establish a new route from the source to the destination. Incorporation of the re-linking technique in existing routing protocol AODV demonstrates an improvement of 10.18% in packet delivery ratio. Experimental analysis indicates a 15% reduction in data loss and 83.23% decrease in latency.

Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO 3 high-k gate oxide and TiN metal gate using quantum modeling

The impact of metal gate work function on the device performance of 22 nm Double-gate FinFET with SiO2 and high-k gate oxide LaAlO3 is studied over a wide range of work functions. Matlab is used to calculate equivalent oxide thickness of high-k material LaAlO3 and simulations are carried out in PADRE device simulator. Quantum-mechanical effects such as Band to Band Tunnelling, Band Gap Narrowing, Carrier-Carrier Scattering are taken care of in the simulation by including the nonlinear drift velocity model and Lombardis transverse field dependent mobility model. We propose a novel device with high-k LaAlO3 and the metal gate TiN. Our results show improvement in on-current, transconductance and degradation in the short channel effects DIBL and subthreshold swing. Using matlab the effect of fin width and underlap length on the fringing capacitance of DG-FinFET is also simulated. To achieve low leakage, optimizations of fin width and underlap length are done via simulations. From our results we propose that a fin width in the range of 6nm-8nm and an underlap length of 3nm are suitable for the novel DG-FinFET structure at 22nm gate length with high-k LaAlO3 and metal gate TiN.