Sangeeta Nakhate

A Compact UWB Microstrip Antenna with Modified Ground Plane for Bandwidth Enhancement

This paper presents a bandwidth enhancing technique using a modified ground plane with diagonal edges, L-shaped slot and parasitic patches with main patch for the design of compact antennas. The proposed low-cost, compact-size rectangular patch antenna on 4.7 cm × 3.6 cm printed circuit board (FR-4) is designed and validated through simulations and experiments. Results show that the ground plane with Lshaped slot in presence of the diagonal cuts at the top corners and the rectangular parasitic patches can increase the bandwidth. Return losses of −23.6 dB and −29.7 dB for the first and second resonant frequencies, respectively, can be achieved when the depth of the diagonal cut is 3 mm, the dimension of each rectangular parasitic patch is 10 mm×3.5 mm, and the L-shaped slot size is 7.5 mm ×2.5mm, providing a 41.27% wider bandwidth than Federal Communication Commission’s(FCC) standard. General Terms Designing of Microstrip Antenna.

High Performance Pipelined Signed 64x64-Bit Multiplier Using Radix-32 Modified Booth Algorithm and Wallace Structure

This paper manly focus on enhancing speed performance of signed multiplication using radix-32 modified Booth algorithm and Wallace Structure. It is designed for fixed length 64x64 bit operands. 3:2and 4:2 Compressor used in Wallace tree structure accumulate partial products. Using both compressor, No. of levels has been reduced that also causes enhancing the speed of multiplier. An efficient VHDL code has been written and successfully synthesized and simulated using Xilinx ISE 9.2i and Model Sim PE Student Edition 10.2c. Proposed pipelined signed 64x64 bit multiplier using radix-32 Booth algorithm and Wallace tree structure provides less delay 1.4 ns and required 87% less number of levels in Wallace tree structure, 76% less total number of Compressor, 70% less generated partial products as compared to conventional multipliers.

High-Performance Pipelined FFT Processor Based on Radix-2 2 for OFDM Applications

This paper introduces high-performance pipelined 256-point FFT processor based on Radix-22 for OFDM communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly’s complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. The proposed design is implemented in VHDL language, synthesized using XST of Xilinx ISE 14.1, and simulated using ModelSim PE Student Edition 10.4a successfully. Also, MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 129.214 MHz after the synthesis process and SQNR is 50.95 dB.

High speed pipelined 64-point FFT processor based on Radix-2 2 for wireless LAN

This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterflys complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. An efficient VHDL code has been written, synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim PE Student Edition 10.4a. Also MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 158.96 MHz after the synthesis process and SQNR 37.02dB for 64 point.

Low power SRAM cell with reduced write PDP and enhanced noise margin

The poor noise margin (NM) and power dissipation has becomes a severe issue in scaled semiconductor device technology. The memory array is major contributors in total power consumption because the most of the time array are utilized for on-chip caches in advanced microprocessors. In this work, the novel eight transistors (8T) cell characterized to improve the read mode noise margin (RMNM), write mode noise margin (WMNM), read power delay product (PDP), write PDP and hold mode power dissipation of SRAM cell. To improve noise margin and hold power, independent read driver and storage latch merged together using stack transistor. The proposed 8T cell have moderate read mode noise performance along with 13.1% lower hold power dissipation and 18% smaller write PDP compared to existing single ended eight transistor SRAM cell at VDD =0.6V. Therefore, the proposed 8T cell could be a suitable alternative for enhanced read mode noise margin and low power SRAM design.

Development of Radiation Hardened By Design (RHBD) of NAND gate to mitigate the effects of single event transients (SET)

Integrated circuits (ICs) operated in harsh environment that consist of various energetic particles is a threat for electronic equipments can provoke temporary errors or soft errors and various undesired effects. This paper presents a Radiation Hardened By Design (RHBD) of NAND gate using dynamic logic at 0.18µm technology is developed with the help of Cadence tool. The Proposed circuit uses hardened precharge circuit with series connected redundant two pull down networks; using two NMOS transistors of same width. The W/L ratio of two transistors relatively increased so as to get discharge path for unwanted charge. One inverter connected to PMOS transistor in feedback loop to mitigate the effect of single event transients (SET) that occurs at critical nodes of gate. Amount of charge collected at any node due to particle strike has been modeled by double exponential current pulse. It is an accurate and efficient prediction of soft errors for SET circuit simulation. Simulation results shows that technique used is more effective for immunity test of SET.

Low standby leakage 12T SRAM cell characterisation

ABSTRACT In this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.

Inductive tuned voltage controlled oscillator for V-band

A highly efficient differential cross coupled voltage controlled oscillator (VCO) with transformer tuning is presented here for V band (60 GHz) application. Here Tuning is done by on chip octagonal transformer which is used as inductive element in LC tank. This transformer tuning scheme gives three bands of frequency to cover 7 GHz bandwidth of 60 GHz unlicensed band and gives low phase noise as compared to inductor based oscillator design. In this method 60 GHz VCO is implemented in UMC 65nm 1P10M CMOS Technology which gives FTR (frequency tuning range) from 55 GHz to 62.4 GHz with phase noise variation -114.5 to -116.5dBc/Hz at 10 MHz offset.

A compact wideband microstrip patch antenna with defected ground plane

In this paper, a compact design and construction of microstrip broadband antenna is proposed. The proposed antenna has the capability of operating between 1.8GHz to 12GHz. The antenna parameter in frequency domain analysis has been investigated to show its capability as an effective radiating element. The simulation results demonstrated good broadband linear transmission performance. A prototype is developed and measurement results are well in agreement. The highest efficiency claimed 92% at 2 GHz and minimum efficiency is 70%. The measured E-plane and H-plane radiation pattern in the entire bandwidth are identical in shape and the direction of maximum radiation is normal to the patch geometry. The designed antenna has a modified ground plane with diagonal edges, L-shaped slot and parasitic patches to main patch for the design of comp act antennas. The proposed low-cost, compact-size rectangular patch antenna on 4.7cm × 3.6cm printed circuit board (FR-4) is designed.