Sanghamitra Roy

Fort-NoCs: Mitigating the Threat of a Compromised NoC

In this paper, we uncover a novel and imminent threat to an emerging computing paradigm: MPSoCs built with 3rd party IP NoCs. We demonstrate that a compromised NoC (C-NoC) can enable a range of security attacks with an accomplice software component. To counteract these threats, we propose Fort-NoCs, a series of techniques that work together to provide protection from a C-NoC in an MPSoC. Fort-NoCss foolproof protection disables covert backdoor activation, and reduces the chance of a successful side-channel attack by “clouding” the information obtained by an attacker. Compared to recently proposed techniques, Fort-NoCs offers a substantially better protection with lower overheads.

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip (NoC) designs. In this paper, we model the effects of these aging mechanisms on NoC components such as routers and links using a novel reliability metric called Traffic Threshold per Epoch (TTpE). We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router microarchitecture that routes the packets along the paths which are both least congested and experience minimum aging stress. After an extensive experimental analysis using real workloads, we observe a 13%, 12.7% average overhead reduction in network latency and Energy-Delay-Product-Per-Flit (EDPPF) and a 10.4% improvement in performance using our aging-aware routing algorithm.

Designing for dark silicon: a methodological perspective on energy efficient systems

The emergence of dark silicon - a fundamental design constraint absent in the past generations - brings intriguing challenges and opportunities in microprocessor design. To gracefully embrace dark silicon, design methodologies must adapt themselves to identify progressive systems that can effectively exploit the growing dark silicon. We demonstrate that relying on traditional design metrics may lead to sub-optimal design choices with the rise of the dark silicon area. We provide a new metric to guide a dark silicon aware system design and propose a stochastic optimization algorithm for dark silicon aware multicore system design. Our design approach shows 7-23% benefit in upcoming technology generations.

An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design

Most practical FPGA designs of digital signal processing applications are limited to fixed-point arithmetic owing to the cost and complexiry of floating-point hardware. While mapping DSP applications onto FPGAs, a DSP algorithm designer, who often develops his applications in MATLAB, must determine the dynamic range and desired precision of input, intermediate and output signals in a design implementation to ensure that the algorithm fidelity criteria are met. The first step in a flow to map MATLAB applications into hardware is the conversion of the floating-point MATLAB algorithm into a fixed-point version. This paper describes an approach to automate this conversion, for mapping to FPGAs by profiling the expected inputs to estimate errors. Our algorithm attempts to minimize the hardware resources while constraining the quantization error within a specified limit

Predicting timing violations through instruction-level path sensitization analysis

In this paper, we present a novel technique for early prediction of timing violations in high-performance pipelined microprocessors. We show that a static instruction in a microprocessor, identified by its Program Counter (PC), is an excellent predictor of an upcoming timing violation. Our analysis combines architectural data collected from real program execution with gate level logic analysis. Exploiting this PC based timing violation predictability, we propose a robust system design that predicts and tolerates timing violations seamlessly in a pipelined microprocessor. Under two different faulty environments, we show 20.9-89.8% and 14.6-80.6% average performance improvements in real programs over other state-of-the-art techniques, respectively.

Analysis and mitigation of NBTI aging in register file: An end-to-end approach

Analysis and tackling of NBTI wearout effects are important design objectives in microprocessor designs. Application induced stress, combined with circuit-architectural design styles creates widely diverging wearout characteristics in a processor datapath. Moreover, in a typical case in desktop computing, different applications can interleave. This interleaving can cause destructive interference in stress patterns leading to substantially worse aging effect than an isolated application. We investigate NBTI wearout degradation in a register file using a comprehensive circuit-architectural analysis of SRAM cells, and show that recently proposed periodic bit inversion is unable to cope with interleaving application induced stress. We propose two novel micro-architecture techniques to mitigate this limitation. Our techniques reduce the Static Noise Margin (SNM) by 2.2X, while improving the degradation uncertainty by 14X over current state-of-the-art techniques. Our overhead analysis shows that both area and power overheads of our proposed technique can be minimal in the context of the reliability improvement it provides.

Topologically homogeneous power-performance heterogeneous multicore systems

Dynamic Voltage and Frequency Scaling (DVFS), a widely adopted technique to ensure safe thermal characteristics while delivering superior energy efficiency, is rapidly becoming inefficient with technology scaling due to two critical factors: (a) inability to scale the supply voltage due to reliability concerns; and (b) dynamic adaptations through DVFS cannot alter underlying power hungry circuit characteristics, designed for the nominal frequency. In this paper, we show that DVFS scaled circuits substantially lag in energy efficiency, by 22–86%, compared to ground up designs for target frequency levels. We propose Topologically Homogeneous Power-Performance Heterogeneous multicore systems (THPH), a fundamentally alternate means to design energy efficient multicore systems. Using a system level CAD approach, we seamlessly integrate architecturally identical cores, designed for different voltage-frequency (VF) domains. We use a combination of standard cell library based CAD flow and full system architectural simulation to demonstrate 11–22% improvement in energy efficiency using our design paradigm.

An MILP-based aging-aware routing algorithm for NoCs

Network-on-Chip (NoC) architectures have emerged as a better replacement of the traditional bus-based communication in the many-core era. However, continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in NoC design. In this paper1, we propose a novel system-level aging model to model the effects of asymmetric aging in NoCs. We observe a critical need of a holistic aging analysis, which when combined with power-performance optimization, poses a multi-objective design challenge. To solve this problem, we propose a Mixed Integer Linear Programming (MILP)-based aging-aware routing algorithm that optimizes the various design constraints using a multi-objective formulation. After an extensive experimental analysis using real workloads, we observe a 62.7%, 46% average overhead reduction in network latency and Energy-Delay-Product-Per-Flit (EDPPF) and a 41% improvement in Instructions Per Cycle (IPC) using our aging-aware routing algorithm.

Efficiently tolerating timing violations in pipelined microprocessors

Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the performance overhead of tolerating these faults. In this paper, we explore several techniques for optimizing instruction scheduling in an Out-of-Order pipeline, exploiting this new perspective in robust system design. Compared to recently proposed stall based techniques for tolerating predictable timing violations, we demonstrate a massive reduction in performance overhead, while supporting correct execution in faulty environments (64-97% across different benchmarks).

Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach

The emergence of power efficient heterogeneous NoCs presents an intriguing challenge in NoC reliability, particularly due to aging degradation. To effectively tackle this challenge, this work presents a dynamic routing algorithm that exploits the architecture level criticality of network packets while routing. Our proposed framework uses a Wearout Monitoring System (to track NBTI effect) and architecture-level criticality information to create a routing policy that restricts aging degradation with minimal impact on system level performance. Compared to the state-of-the-art BRAR (Buffered-Router Aware Routing), our best scheme achieves 38%, 53% and 29% improvements on network latency, system performance and Energy Delay Product per Flit (EDPPF) overheads, respectively.