Sani Irwan Md Salim

3-D Biped Robot Walking along Slope with Dual Length Linear Inverted Pendulum Method (DLLIPM)

A new design method to obtain walking parameters for a three-dimensional (3D) biped walking along a slope is proposed in this paper. Most research is focused on the walking directions when climbing up or down a slope only. This paper investigates a strategy to realize biped walking along a slope. In conventional methods, the centre of mass (CoM) is moved up or down during walking in this situation. This is because the height of the pendulum is kept at the same length on the left and right legs. Thus, extra effort is required in order to bring the CoM up to higher ground. In the proposed method, a different height of pendulum is applied on the left and right legs, which is called a dual length linear inverted pendulum method (DLLIPM). When a different height of pendulum is applied, it is quite difficult to obtain symmetrical and smooth pendulum motions. Furthermore, synchronization between sagittal and lateral planes is not confirmed. Therefore, DLLIPM with a Newton Raphson algorithm is proposed to solve these problems. The walking pattern for both planes is designed systematically and synchronization between them is ensured. As a result, the maximum force fluctuation is reduced with the proposed method.

The Solution of Stereo Correspondence Problem Using Block Matching Algorithm in Stereo Vision Mobile Robot

This paper presents the solution of stereo correspondence problem occur in comparing stereo images on stereo vision mobile robot using block matching algorithm. The algorithm is using Sum of Absolute Differences (SAD). Left image works as a reference block to the right image and the output is disparity mapping with the left coordinate system. The stereo vision baseline is based on horizontal configuration. The block matching technique is briefly described with the performance of its output. The curve fitting tool will determine the range of each obstacle detected in disparity mapping. The programming activities are using Matlab software starting from capturing images until navigation of mobile robot.

Door Sensors for Automatic Light Switching System

Door sensor for automatic lighting control is widely being developed for energy saving and security purposes. An infrared door sensor based on electrical and electronics combinational circuit technology is used to develop the automatic light switching system. The automatic light switching system will lead to energy saving and efficient energy usage which could benefit every single individual. Furthermore, the system is developed with safety enviroment when switching ‘ON’ or ‘OFF’ the light during the room occupancy or unoccupancy. Apart from safety enviroment, it also comprises manual switching in case user needs to have light during the day. Basically, this system is designed to be installed in the restroom.

Hexagon-Diamond Grid System for Motion Tracking

Based on the block-matching motion vector estimation techniques, a grid system using the block-based technique is proposed for motion tracking in video sequences. The technique is known as hexagon-diamond grid system (HDGS). The HDGS has a large hexagon and small diamond search pattern based on block-matching motion tracking characteristics. The large hexagon search pattern will capture the motion in a particular block of the large region before the small diamond search pattern takes place. The small diamond design pattern is to provide accuracy and to obtain the best motion vector coordinate for motion tracking purposes. This motion vector coordinate can be used as a reference to track the motion in the images. The vector coordinate will determine whether the object is moving toward the horizontal or vertical plane. This will help to determine the region of interest to be examined based on the motion vector coordinate. Besides the motion vector measurement, the point signal noise-to-ratio (PSNR) is also applied to measure the quality of the video.

Distance approximation using pivot point in narrow phase collision detection

Discrete and Continuous Collision Detection is two common fields in Collision Detection research area where it helps to determine time and point of contact when two object intersect. Each technique increase speed and accuracy of the simulation itself but depending on application, we need to have specific solution of collision detection technique. Most computer games and simulation maintain speed as the main important elements while others such as medical and mechanical simulation needs to have a very high precision collision detection technique. Thus, an algorithm for the optimal distance computation algorithm for continuous collision detection is shown in this paper. The basic idea is to use an AABB for both object triangles and creating a moveable origin point called Dynamic Origin Point (DyOP). DyOP created by using minimum and maximum point of both AABBs where it dynamically changes whenever the object move. This is a novel algorithm that works better than the previously known Gilbert Keerthi-Johnson algorithm and Lin-Canny algorithm where it helps to reduce the complicated test and implementation. We have shown that our technique is performed faster than the previous algorithms by increasing speed and nearly approximate the good distance between two nearly intersected triangles.

PWM controller design of a hexapod robot using FPGA

Motor control mechanism on a robotic platform has been dominated by microcontroller-based system for the past decade. With the advancement of the reconfigurable hardware platforms such as field programmable gate array (FPGA), such control mechanism is being ported to the platform in order to improve efficiency and achieves higher performance. This paper presents the FPGA implementation of the servomotor control technique which is applied for a six-legged robot platform. The hexapod robot consisted of 18 continuous servomotors with 3 servos on each leg. Each of the servomotors is assigned with single pulse width modulation (PWM) output and could be individually controlled by the main controller. To enable smooth movement of the hexapod, all the PWM output are synchronized based on a simple tripod gait movement. The servo motor controller is implemented in the Spartan-3 FPGA chip and the hardware design is described in Verilog Hardware Description Language (HDL). The controller design is simulated and verified using Xilinxs ISE Simulator (ISim). Initial hardware implementation also has been conducted on several basic movements on the hexapod such as standing-up, forward and backward movement. Overall, the implementation of the servomotor controller in an FPGA has offered several advantages in terms of circuit design flexibility and simultaneous command executions when compared to conventional microcontroller-based system.

Two-pass assembler design for a reconfigurable RISC processor

Hardware software co-design plays a crucial part in the embedded processor development especially with the current advancement of reconfigurable platforms. The reconfigurability features offered by platforms such as Field Programmable Gate Array (FPGA) has permitted the modification of the internal processor architecture with lower cost and higher performance. While the hardware architecture could be changed through various methods, the modifications need to be complemented with a compatible assembler that suits the amended architecture. This paper presents a two-pass assembler design technique that adapts to any instruction set architecture (ISA) modifications being applied on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to include new instruction sets. The assembler is developed based on two-pass approach and the assembling process would generate a coefficient file that is used as initialization files during the FPGA implementation of the processor core. The assemblers have been successfully developed with correct output format and verified during the FPGA implementation using Xilinx Spartan-3AN board.

Customized instruction set simulation for soft-core RISC processor

This paper presents the instruction set simulation process for soft-core Reduced Instruction Set Computer (RISC) processor. The aim of this paper is to provide reliable simulation platform in creating customizable instruction set for Application Specific Instruction Set Processor (ASIP). The targeted RISC processor is based on basic 8-bit PIC16C5X-compatible processor where the architecture is reconfigurable through Hardware Description Language (HDL). Instruction set architecture (ISA) has been modified in term of instruction width and machine instruction. Memory address remapping algorithm is introduced to remap the memory address to correct physical memory address due to memory banking scheme being applied. A total number of 34 instruction sets are simulated and verified its operations. Selected instruction set has been reconfigured from its original operation to demonstrate the ability to modify current instruction set to suit certain specialized application. The simulation is done using a Java-based CPU architecture simulation program and data movements at file register array and memory registers are monitored to verify the correct working operation of each instruction set. The instruction set simulation process is proved capable to be the starting point in creating a reconfigurable RISC processor with customized instruction set, inline with ASIP methodology.

Development of fuzzy logic controller on a magnetic bearing system

A magnetic bearing system is a device that uses electromagnetic forces to support a rotor without mechanical contact. The force exerted on the rotor by an active magnetic bearing is determined by the current flow in the magnet coil. The focus of this project will be on the stability and control of the MBC 500 system test bed constructed by Magnetic Moments Incorporated. The MBC 500 system contains a stainless steel shaft or rotor, which can be levitated using eight horseshoe electromagnets, four at each end of the rotor. A controller, which is able to stabilize the position of the rotor by varying the electromagnet forces produced by the electromagnets at the end of the shaft will be developed. Here, a rotor is assumed as a rigid body. A fuzzy logic controller as an alternative control strategy using Sugenos inference method will be designed in controlling and stabilizing the position of the rotor for the system.

One-pass assembler design for a low-end reconfigurable RISC processor

Implementation of processor core on a programmable device such as Field Programmable Gate Array (FPGA) has been widely adopted by researchers due to its flexibility and hardware reconfigurability. However, with processor design is a tightly integrated development of hardware and software, changes in the processors hardware architecture would require the same alterations being made on the software side. This paper presents a one-pass assembler design technique that adapts to modifications of the instruction set architecture (ISA) on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to perform the instruction set extension. A lexical analyzer and tokenization technique is adopted in the assembler development with several hash tables are setup to store all the tokens. The assembler would generate a coefficient file that contained all the translated instruction codes sourced from an assembly program. The coefficient file then is initiated in the memory module of the RISC processor core using Xilinx Spartan-3AN FPGA board. Based on the simulation results, the assemblers have been successfully developed with working coefficient file output format that matched to the ISA modifications.