Sani R. Nassif

Modeling and analysis of manufacturing variations

Process-induced variations are an important consideration in the design of integrated circuits. Until recently, it was sufficient to model die-to-die shifts in device performance, leading to the well known worst-case modeling and design methodology. However, current and near-future integrated circuits are large enough that device and interconnect parameter variations within the chip are as important as those same variations from chip to chip. This presents a new set of challenges for process modeling and characterization and for the associated design tools and methodologies. This paper examines the sources and trends of process variability, the new challenges associated with the increase in within-die variability analysis, and proposes a modeling and simulation methodology to deal with this variability.

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of more than 100times compared to regular Monte Carlo. To the best of our knowledge, this is the first time such a methodology is applied to the analysis of SRAM designs

A multigrid-like technique for power grid analysis

Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at ever lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. We propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very efficient as well as suitable for both DC and transient analysis of power grids.

Fast power grid simulation

The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance limiting factors [1, 2, 3], then their analysis is important in order to (1) predict the performance and (2) improve the performance if necessary. Thus, there is a clear need for new efficient, in terms of both execution time and memory, techniques for power grid analysis. This paper discusses the modeling of power grids and proposes a new PDE-like multigrid method for the simulation of power grids. The proposed method is very efficient and suitable for both DC and transient simulation of power grids.

Random walks in a supply network

This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transient analysis. The method has the desirable property of localizing computation, so that it shows massive benefits over conventional methods when only a small part of the grid is to be analyzed (for example, when the effects of small changes to the grid are to be examined). Even for the full analysis of the grid, experimental results show that the method is faster than existing approaches and has an acceptable error margin. This method has been applied to test circuits of up to 2.3M nodes. For example, for a circuit with 70K nodes, the solution time for a single node was 0.42 sec and the complete solution was obtained in 17.6 sec.

Impact of interconnect variations on the clock skew of a gigahertz microprocessort

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in todays gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.

Power grid analysis benchmarks

Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent experience from the placement [1] and routing [2] areas suggests that the ready availability of realistic industrial-size benchmarks can energize research in a given area, and can even lead to significant breakthroughs. To this end, we are making a number of power grid analysis benchmarks available for the public. These are all drawn from real designs, and vary over a reasonable range of size and difficulty thereby making studies of algorithm complexity possible. This paper documents the format for the various benchmarks, and give details for their access.

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area.

Statistical analysis of SRAM cell stability

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extremes

Benefits and costs of power-gating technique

Power-gating is a technique for saving leakage power by shutting off the idle blocks. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and may make the technique not worth the effort. In this paper, we report on our study of the benefits and costs of the power-gating technique in terms of power, area, and performance. We model and analyze several strongly related parameters such as sleep-transistor size, decap area, and supply voltage level. We also report on our experiments to demonstrate how the gated area, circuit behavior and power mesh granularity affect the power gating technique at the system level. Experimental results show that, by compromising 4% of the total area and 5% of the dynamic power, we can achieve 47% leakage power saving while maintaining the same performance. With technology scaling down, the saving is significant. We conclude that we can benefit from the power-gating technique in future technology nodes.