Sanjay Desai

The architecture of the LR33020 graphX processor: a MIPS-RISC based X-terminal controller

The architecture and implementation of a MIPS-RISC-based application-specific microprocessor designed specifically for X-Window terminals is described. It consists of a graphics coprocessor integrated with a MIPS-1 (R3000)-compatible CPU core along with system-level functions found in a typical X-Terminal. The design of the graphics coprocessor has been optimized for accelerating low-level graphics operations typical in X-Windows applications. It is implemented as coprocessor 2. A set of coprocessor 2 graphics instructions process pixel data fetched by dedicated DMA channels through a high-bandwidth (64 b) memory interface. The combination of the graphics coprocessor and high-bandwidth memory interface result in a very high performance. The presence of system-level functions on the same die as the CPU and graphics engine make for a very highly integrated processor.<<ETX>>

The architecture of the LR33000: a MIPS compatible RISC processor for embedded control applications

RISC processors have been widely accepted in the performance driven segments of the reprogrammable computer market such as workstations and file servers. However, these chips, despite their high levels of performance, do not adequately address embedded control applications. A description is given for the macro- and micro-architecture of the LR 33000, a single chip, 50 MHz, RISC processor, which was designed and optimized for embedded control applications while retaining both software compatibility with the MIPS-1 instruction set and a high level of performance. The optimization for embedded control applications was done by focusing on the following goals: minimizing the overall system cost by increasing the level of integration, simplifying the system design, and reducing the power consumption.<<ETX>>

A Tightly Coupled Pipelined Graphics Coprocessor Integrated With A RISC CPU

This paper describes lhe architecture and implementation of a graphics coprocessor integrated with a MIPS-1 (R3000) compatible CPU core. The design of the graphics coprocessor has been oprimiscd for accelerating low level graphics operations typical in X Windows applications. It has been implemented us coprocessor 2 using the coprocessor interface available on the CPU core. A set of specifically designed coprocessor 2 graphics instructions execute on the coprocessor and process pixel data fetched by dedicated DMA channels through a high bandwidth memory interface. The combination of the graphics coprocessor und high Oundwidlh memory interface result in a very high perfnrmcince.