Sankaran Aniruddhan

CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits

A tuned-input tuned-output (TITO) VCO utilizes two resonant-tanks to achieve a low measured phase noise of 130.5 dBc/Hz @ 1 MHz offset from 2.5 GHz center frequency. Improvement in phase noise is achieved with comparable power consumption and tuning range compared to a cross-coupled VCO topology. A TITO cell similar to that in the VCO is used as a common-source amplifier in a current-reuse configuration cascaded with a -boosted common-gate amplifier to realize a high gain (20 dB), low power (2.7 mW) LNA. A technique to improve the linearity of the current-reuse LNA is also presented.

A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor

Cellular phones in emerging markets have continued to grow with multimedia features such as MP3 playback, video encode and decode, high-resolution cameras and web browsing. To efficiently support multimedia functionalities, highperformance modems are required. There is also a strong demand to reduce the cellular phone PCB footprint, and to enable integration of peripheral devices such as Bluetooth and Wireless LAN. Previously reported SoC or SiP solutions have integrated a GPRS/EDGE radio with modem and limited multimedia capabilities [1–4]. This paper presents a multimode UMTS/GSM RF transceiver integrated with a digital baseband having advanced multimedia functionalities. The SoC, designed in 65nm digital CMOS, supports quad-band GSM/GPRS/EDGE (3GPP R4, Class 12) and tri-band UMTS/WCDMA (3GPP R99, R5 cat 5/6), including band 1–2–4–5–6–8–9–10.

A lateral-BJT-biased CMOS voltage-controlled oscillator

A fully integrated 5 GHz differential LC-VCO using a lateral pnp current source in 250nm CMOS is presented. The lateral PNP device structure and its characteristics reviewed. The use of lateral BJT current sources in VCOs reduces flicker noise up-conversion, which is a critical need for systems with stringent close-in phase noise specifications. The VCO achieves a simulated phase noise of -93dBC/Hz at 100kHz offset and draws 4mA from a single 2.5V power supply; the VCO tuning range is 18%.

A fully-differential CMOS Clapp VCO for IEEE 802.11a applications

A fully integrated 5-6GHz differential VCO derived from the classical Clapp topology is presented in 180nm CMOS. The Clapp architecture and its characteristics are reviewed, and the location of critical portions of the circuit such as the LC-tank and varactors is discussed. The use of a Clapp VCO topology allows a larger voltage swing, which improves spectral purity and phase noise. The use of a symmetrical inductor for differential operation results in a higher Q with lower area, while providing common-mode noise rejection. The VCO achieves a simulated phase noise of -98dBc/Hz @ 100kHz & -123.1dBc/Hz @ 1MHz offsets, and draws 5mA from a 1.8V power supply. A high tuning range of 18% and FOM of 189dBc/Hz are reported. Finally, system-level simulations of a frequency synthesizer for the IEEE 802.11a bands using the Clapp VCO are presented

Directional coupler with high isolation bandwidth using electrical balance

A directional coupler using edge coupled lines is designed and fabricated on a two-layer PCB with isolation being achieved through electrical balance. Measured results show 4dB coupling and 34dB isolation at a frequency of 2.5GHz with 16% matching bandwidth (-10dB). Isolation varies between 31dB to 36dB in the 2.3GHz to 3GHz frequency range.

A Taylor series approximation technique for self-interference cancellation in full-duplex radios

Full-duplex (FD) wireless communication is gaining increasing attention of the wireless industry because of the potential doubling of spectral efficiency. Radio design of an FD transceiver is a key aspect to its realization. The major impediment in realizing an FD radio is the self interference (SI). The received self interference is a filtered version of the transmitted signal, the filter (SI filter) being caused by the multiple transmit paths through the circuit board (or silicon substrate) and the wireless channel. Current techniques for suppressing SI rely on mimicking the SI filter partly in the RF domain (using multiple length RF traces on a PCB) and partly in the digital domain by adaptive techniques. This paper proposes a novel SI cancellation technique, based on Taylor series expansion of the delayed signal, that results in linearizing the delayed self-interference component of the transmitted signal. Linearization not only aids the practicality of analog cancellation by reducing the form factor, but also results in a simple SI filter model in the digital domain. In this paper, in addition to deriving the generic form of the SI filter, we provide experimental evidence for the same.

A Compact Mixer-First Receiver With >24 dB Self-Interference Cancellation for Full-Duplex Radios

This letter presents a single-channel full-duplex receiver with tunable self-interference (SI) cancelling capability through LO phase shifting. The receiver takes advantage of high linearity of the passive mixer-first architecture to eliminate SI without degrading sensitivity due to inter-modulation distortion. The proposed receiver exhibits a DSB noise figure of 8.6-12.5 dB over an operating frequency range of 800 MHz-1.7 GHz. It achieves >70.5 dB SINDR in 16.25 MHz RF signal bandwidth at -18 dBm input SI power. The receiver is implemented in a 130 nm CMOS process and occupies an area of 0.63 mm2.

Replica bias scheme for efficient power utilization in high-frequency CMOS digital circuits

Digital circuits exhibiting rail-to-rail voltage swings display large spreads in current consumption and delay over variations in process, voltage and temperature (PVT). A circuit technique is proposed to enable optimal current consumption and low delay distribution in high frequency digital circuits. A typical RF application is chosen at 5 GHz frequency, for which a divider is designed and simulated in a UMC 130nm CMOS process. With the proposed scheme, the circuit shows up to 52% reduction in current, while the relative variation in delay over PVT reduces by 70%.

Quadrature generation techniques in CMOS relaxation oscillators

Shunt and series-coupling techniques for quadrature generation are applied to CMOS relaxation oscillators. The 2.4GHz quadrature oscillators are designed and simulated in a UMC 0.18µm CMOS process. The shunt-coupled oscillator consumes a current of 12mA from a supply of 1.8V and achieves a phase noise of −99.4dBc/Hz @ 1MHz offset. The series-coupled oscillator consumes a current of 16mA from the 1.8V supply and achieves a phase noise of −98.3dBc/Hz @ 1MHz offset. For a systematic mismatch of 1%, the quadrature phase error of the shunt-coupled and series-coupled circuits are 0.55° and 0.1° respectively.

A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing

A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18-μm CMOS locks in 40 μs and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1° and the phase noise spectral density is -116.8 dBc/Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are -83 dBc and -105 dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively.