Sanshiro Shishido

A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixel Readout and no Static Bias Current

Low-power operation of CMOS imagers using a low voltage (around IV or less) compatible with deep submicron logic circuits enables new imager applications, such as disposable medical cameras and autonomous wireless security cameras on a chip. Pulse width modulation (PWM) is promising for this purpose. A PWM pixel can convert light intensity to a digital pulse width by using an in-pixel comparator with a low power-supply voltage without any degradation of signal-to-noise ratio (SNR). In this paper, we propose and demonstrate a low-power dynamic pixel readout in-pixel comparators(DPR) scheme with CGA PWM pixels based on dynamic operation of in-pixel comparators. DPR requires no static bias current even in the pixel readout. The power dissipation of the pixel array is dramatically reduced by 1 to 2 orders of magnitude compared with using normal static pixel readout (SPR).

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

Polarization Analyzing Image Sensor with On-Chip Metal Wire Grid Polarizer in 65-nm Standard Complementary Metal Oxide Semiconductor Process

A polarization analyzing complementary metal oxide semiconductor (CMOS) image sensor with a fine on-chip metal wire grid polarizer in the 65-nm standard process is presented. The extinction ratio is an important characteristic for a polarizer that depends largely on the feature size of the metal wire grid pitch and the fabrication CMOS process. To improve the extinction ratio, we designed and fabricated a sensor chip in the 65-nm process. The design rules of the 65-nm process realize the fine metal wire grid pitch compared with the wavelength of visible light. Improvement of extinction ratio is expected by such a fine structure. With the fabricated sensor, an extinction ratio greater than 40 was achieved. The difference between the measured value and the simulation value of the extinction ratio, and pixel crosstalk of the fabricated sensor are discussed.

A low-voltage PWM CMOS imager with small pixel size using an in-pixel gate-common comparator

We propose a new pixel structure of pulse-width-modulation (PWM) CMOS active pixel sensor with a small pixel size performing a pixel-level single-slope A/D conversion to realize a low and single power supply operation. The pixel is composed of only three transistors without pixel-circuit sharing, and has a gate-common amplifier that compares a photodiode voltage on the gate node with a ramp signal on the source for A/D conversion. We have fabricated a 128×96-pixel prototype imager with an on-chip ramp generator and bootstrap circuits in a 0.35-µm CMOS technology, and successfully demonstrated image acquisition with a 1.4-1.8-V single power supply.

CMOS image sensor for recording of intrinsic-optical-signal of the brain

Intrinsic optical signal (IOS) indicates activities of cerebral cortical neurons in the optical imaging method, which is one of the in vivo recording methods of activities of cerebral cortical neurons. We propose the IOS imaging method for craniotomy procedure such as diagnostic use of epilepsy surgery. We designed a prototype CMOS image sensor device using 0.35-µm CMOS standard process for in vivo IOS imaging. The sensor device enables multi-functional recording of brain activities such as IOS, EEG, area image, electrical stimulation in order to improve reliability of diagnosis and allows simple measurement setup. Preliminary experiments using the fabricated device are demonstrated to detect hemoglobin filled in a blood vessel phantom.

A Low-Voltage Complementary Metal Oxide Semiconductor Image Sensor Using Pulse-Width-Modulation Scheme for Biomedical Applications

In this paper, we present a detailed characterization and evaluation of the performance of a source-modulated pulse-width-modulation (PWM) scheme image sensor designed for biomedical applications. The image sensor is based on the PWM readout scheme that we proposed in a previous study. The PWM sensor is equipped with a novel three-transistor PWM pixel to realize low-voltage and high-resolution on-chip bioimaging. We explain the sensor operation and capability of the low-voltage PWM scheme by comparing it with a conventional active pixel sensor (APS). We successfully demonstrate the function of the image sensor with a 1.35 V single power supply voltage. We discuss the characteristics in terms of the effect of the IR drop, tradeoffs, and our evaluation of the capability of the PWM sensor of pixel size for biomedical applications.

Demonstration of a low-voltage three-transistor-per-pixel CMOS imager based on a pulse-width-modulation readout scheme employed with a one-transistor in-pixel comparator

To realize a low-voltage CMOS imager with a small pixel size, we have proposed a new pixel structure composed of only three transistors without any circuit sharing technique. The pixel has a gate-common transistor that compares a photodiode voltage on the gate node with a ramp signal on the source node to perform a single-slope A/D conversion based on a pulse-width-modulation pixel-reading scheme. The large gain of the in-pixel comparator contribute to the small input-referred noise and surpress column-to-column fixed-pattern-noise (FPN). Pixel-to-pixel FPN is suppressed by a feedback reset. Our CMOS imager can lower the operating voltage with less degradation of the dynamic range than that of ordinary active pixel sensors. We have fabricated a 128×96-pixel prototype sensor with an on-chip ramp generator and bootstrap circuits in a 0.35-&mgr;m CMOS technology, and successfully demonstrated its operations with a 1.5-V single power-supply voltage.