Sarah Boyd

SleepWalker: A 25-MHz 0.4-V Sub-

Integrated circuits for wireless sensor nodes (WSNs) targeting the Internet-of-Things (IoT) paradigm require ultralow-power consumption for energy-harvesting operation and low die area for low-cost nodes. As the IoT calls for the deployment of trillions of WSNs, minimizing the carbon footprint for WSN chip manufacturing further emerges as a third target in a design-for-the-environment (DfE) perspective. The SleepWalker microcontroller is a 65-nm ultralow-voltage SoC based on the MSP430 architecture capable of delivering increased speed performances at 25 MHz for only 7 μW/MHz at 0.4 V. Its sub-mm2 die area with low external component requirement ensures a low carbon footprint for chip manufacturing. SleepWalker incorporates an on-chip adaptive voltage scaling (AVS) system with DC/DC converter, clock generator, memories, sensor and communication interfaces, making it suited for WSN applications. An LP/GP process mix is fully exploited for minimizing the energy per cycle, with power gating to keep stand-by power at 1.7 μW. By incorporating a glitch-masking instruction cache, system power can be reduced by up to 52%. The AVS system ensures proper 25-MHz operation over process and temperature variations from -40 °C to +85 °C, with a peak efficiency of the DC/DC converter above 80%. Finally, a multi-Vt clock tree reduces variability-induced clock skew by 3 × to ensure robust timing closure down to 0.3 V.

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The vision of the Internet of Things with ambient intelligence calls for the deployment of up to a trillion connected wireless sensor nodes (WSNs). Minimizing the carbon footprint of each node is paramount from the sustainability perspective. In ultra-low-power applications, the life-cycle carbon footprint results from a complex balance between both embodied and use-phase energies [1]. The embodied energy arises mainly from CMOS chip manufacturing, and is essentially proportional to die area. Use-phase energy depends on both active and sleep-mode power, because of long stand-by periods in WSNs. In this paper, we present an ultra-low-power 25MHz microcontroller SoC that fully exploits the versatility of a 65nm CMOS process with a low-power/general-purpose (LP/GP) transistor mix (dual-core oxide) to obtain: i) 7μW/MHz active power consumption due to a 0.4V ultra-low-voltage (ULV) thin-core-oxide (GP) CPU supplied by a 78%-efficiency embedded DC/DC converter; ii) 0.66mm2 die area for low embodied energy due to a compact converter design and a dual-VDD architecture, enabling the use of the foundrys 1V high-density 6T SRAM bitcell; and, iii) 1.5μW sleep-mode power due to body-biased sleep transistors embedded into the converter and thick-core-oxide (LP) MOSFETs for retentive SRAM and always-on peripherals (AOP). Moreover, an on-chip adaptive voltage scaling (AVS) system controlling the converter ensures safe 25MHz operation at ULV for all PVT conditions. A multi-Vt clock tree is also proposed to achieve reliable timing closure with low-power SoC features. Finally, a glitch-masking instruction cache (I

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) is implemented to reduce the access power of the 1V program memory (PMEM).

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A life cycle inventory for comparative assessment of assorted semiconductor device types is assembled using a library of process step-related information. In this paper, we present the structure of this library of energy use, material inputs and emissions data at the process equipment-level and facilities-scale, normalized per wafer. Selected results from a case study of a 130nm node CMOS device are presented and compared with a previous study of a comparable chip. Comparative production impacts of 6-layer and 8-layer CMOS devices are shown

Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes

With increasing sophistication of products, there is a general trend towards higher purity (lower tolerances) in materials and parts. The purification of input materials and the need to create low-entropy environments in manufacturing lead to significant energy and materials use - referred to as secondary materialization. In this article we explore secondary materialization in semiconductor manufacturing by characterizing energy use trends for three cases: cleanrooms, producing ultrapure water (UPW), and purifying elemental gases. For purification of water and elemental gases, increasing purity standards are correlated with dramatic increases in energy use. For cleanrooms, while electricity use per square foot tends to increase with increasing air purity, this growth is cancelled by the evolution towards larger wafers and mini-environments. The net result is reductions in energy use per area of wafer processed when moving from 200 mm to 300 mm wafer processing. Given the continuing trend towards higher purity standards and growth in high-tech manufacturing, the high growth in secondary energy use suggests that the characterization and management of energy and materials use for purification deserves increased attention.

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes

Solid state drives (SSDs) show potential for environmental benefits over magnetic data storage due to their lower power consumption. To investigate this possibility, a life-cycle assessment (LCA) of NAND flash over five technology generations (150 nm, 120 nm, 90 nm, 65 nm, and 45 nm) is presented to quantify environmental impacts occurring in flash production and to view their trends over time. The inventory of resources and emissions in flash manufacturing, electricity generation, and some chemicals are based on process data, while that of fab infrastructure, water and the remaining chemicals are determined using economic input-output life-cycle assessment (EIO-LCA) or hybrid LCA. Over the past decade, impacts have fallen in all impact categories per gigabyte. Sensitivity analysis shows that the most influential factors over the life-cycle global warming potential (GWP) of flash memory are abatement of perfluorinated compounds and reduction of electricity-related emissions in manufacturing. A limited comparison between the life-cycle energy use and GWP of a 100 GB laptop SSD and hard disk drive shows higher impacts for SSD in many use phase scenarios. This comparison is not indicative for all impact categories, however, and is not conclusive due to differences in boundary and functional unit.

Life Cycle Inventory of a CMOS Chip

The exponential growth of the semiconductor industry raises serious environmental concerns. Accurate life-cycle data are critical for both appropriate product eco-design and life-cycle analysis (LCA) of new electronic applications. Previous semiconductor LCA efforts were based on generic studies dealing with an average component description such as microprocessors, DRAM or Flash memories without taking into account the broad application range of each component. In this paper, we show that accurate life-cycle data can only be obtained with an application-aware approach. We demonstrate this with a life-cycle energy evaluation of microprocessors for five different applications: from high-performance 32 nm CPUs for servers and laptops to low-power 45 nm processors for set-top boxes and smart phones to ultra-low-power 130 nm MCUs for wireless sensors. For each category, we model the energy of the CMOS processing steps for integrated circuit (IC) fabrication as well as the use phase energy demand including both active and stand-by modes. Results show that life-cycle energy varies by a factor 20000× between the high-performance and the ultra-low-power ends.

Case studies in energy use to realize ultra-high purities in semiconductor manufacturing

A methodology to perform a hybrid approach to evaluate semiconductor life cycle impacts is developed. This methodology uses (i) bottom-up process models and data to develop inventories for semiconductor manufacturing, and for specialty semiconductor chemicals items and (ii) an economic input-output method for generic inventory items. The approach attempts to overcome several semiconductor LCA (life cycle assessment) challenges and is illustrated through a case study in life cycle environmental impacts of an interconnect module in a logic device.

Life-Cycle Assessment of NAND Flash Memory

One of the goals of The Sustainability Consortium (TSC) is to bridge the divide between rigorous scientific analysis of the life cycle of consumer goods and the ability of the purchaser/ consumer to absorb and act on the environmental impact information provided from such an analysis. TSC has approached this issue through the development of the Sustainability Measurement and Reporting System (SMRS), which describes a process that facilitates the communication of environmental impacts derived from life cycle analysis to a broader lay audience. Based on ISO 14025 Type III environmental declarations, the SMRS provides the common rules for reporting impacts and creates a product declaration that can underpin any number of consumer communication modes. This paper presents the SMRS methodology and its application to laptop computers.

Application-aware LCA of semiconductors: Life-cycle energy of microprocessors from high-performance 32nm CPU to ultra-low-power 130nm MCU

There is growing need for effective and efficient environmental assessment tools for information technology (IT) products. This paper presents a streamlined life cycle analysis (LCA) methodology using a screening and triage approach. The methodology is applied to the case study of liquid crystal displays (LCDs). Global warming potential uncertainty is reduced by identifying and resolving uncertainty around key drivers of impact. The resolution of impact continues until a meaningful level of reduction of uncertainty is achieved, such as the ability to discriminate one class of LCD from another.