Sarah L. Harris

A collisional perspective on quadrupedal gait dynamics.

The analysis of terrestrial locomotion over the past half century has focused largely on strategies of mechanical energy recovery used during walking and running. In contrast, we describe the underlying mechanics of legged locomotion as a collision-like interaction that redirects the centre of mass (CoM). We introduce the collision angle, determined by the angle between the CoM force and velocity vectors, and show by computing the collision fraction, a ratio of actual to potential collision, that the quadrupedal walk and gallop employ collision-reduction strategies while the trot permits greater collisions. We provide the first experimental evidence that a collision-based approach can differentiate quadrupedal gaits and quantify interspecific differences. Furthermore, we show that this approach explains the physical basis of a commonly used locomotion metric, the mechanical cost of transport. Collision angle and collision fraction provide a unifying analysis of legged locomotion which can be applied broadly across animal size, leg number and gait.

MIPSfpga: Hands-on learning on a commercial soft-core

In this paper, we introduce a course centered around MIPSfpga, an unobfuscated commercial MIPS soft-core processor made available by Imagination Technologies for academic purposes. The course focuses on hands-on learning that emphasizes System on Chip (SoC) design and hardware-software codesign. Students first study MIPS computer architecture and microarchitecture and then learn and experiment with the MIPSfpga system. A set of labs guides the students in setting up the MIPS soft-core processor on a field-programmable gate array (FPGA) and running and debugging programs on the core in simulation and in hardware. Students then modify the MIPSfpga system to interact with various peripheral devices and complete a self-directed final project.

Linking gait dynamics to the mechanical cost of legged locomotion

For millenia, legged locomotion has been of central importance to humans for hunting, agriculture, transportation, sport, and warfare. Today, the same principal considerations of locomotor performance and economy apply to legged systems designed to serve, assist, or be worn by humans in urban and natural environments. Energy comes at a premium not only for animals, wherein suitably fast and economical gaits are selected through organic evolution, but also for legged robots that must carry sufficient energy in their batteries. Although a robots energy is spent at many levels, from control systems to actuators, we suggest that the mechanical cost of transport is an integral energy expenditure for any legged system—and measuring this cost permits the most direct comparison between gaits of legged animals and robots. Although legged robots have matched or even improved upon total cost of transport of animals, this is typically achieved by choosing extremely slow speeds or by using regenerative mechanisms. Legged robots have not yet reached the low mechanical cost of transport achieved at speeds used by bipedal and quadrupedal animals. Here we consider approaches used to analyze gaits and discuss a framework, termed mechanical cost analysis, that can be used to evaluate the economy of legged systems. This method uses a point mass perspective to evaluate the entire stride as well as to identify individual events that accrue mechanical cost. The analysis of gait began at the turn of the last century with spatiotemporal analysis facilitated by the advent of cine film. These advances gave rise to the “gait diagram,” which plots duty factors and phase separations between footfalls. This approach was supplanted in the following decades by methods using force platforms to determine forces and motions of the center of mass (CoM)—and analytical models that characterize gait according to fluctuations in potential and kinetic energy. Mechanical cost analysis draws from these approaches and provides a unified framework that interprets the spatiotemporal sequencing of leg contacts within the context of CoM dynamics to determine mechanical cost in every instance of the stride. Diverse gaits can be evaluated and compared in biological and engineered systems using mechanical cost analysis.

Practical experiences based on MIPSfpga

In this paper we describe how to use MIPSfpga, a soft-core MIPS processor, to teach undergraduate and masters-level computer architecture courses. The most recent release of MIPSfpga (version 2.0), consists of three packages: the MIPSfpga Getting Started Guide, MIPSfpga Labs, and MIPSfpga System on Chip. After giving an overview of these packages, we provide examples of how to integrate MIPSfpga into curricula by describing three teaching experiences that used the MIPSfpga packages: an undergraduate course at the University Complutense of Madrid, a course at the Technical University of Darmstadt, and several seminars held at various Russian research centers and universities. MIPSfpga enabled students to bridge the gaps between theoretical concepts, hands-on practice, and industrial cores by allowing them to explore, modify, and test the MIPS core and system with the support of commercial compilers and tools.

9 – I/O Systems

The role of the operating system in computer I/O is to manage and control I/O operations and I/O devices. Although related topics appear in other chapters, here we bring together the pieces to paint a complete picture. In this chapter we describe I/O structure, devices, device drivers, caching, and terminal I/O. Exercises 13.1 When multiple interrupts from different devices appear at about the same time, a priority scheme could be used to determine the order in which the interrupts would be serviced. Discuss what issues need to be considered in assigning priorities to different interrupts. Answer: A number of issues need to be considered in order to determine the priority scheme to be used to determine the order in which the interrupts need to be serviced. First, interrupts raised by devices should be given higher priority than traps generated by the user program ; a device interrupt can therefore interrupt code used for handling system calls. Second, interrupts that control devices might be given higher priority than interrupts that simply perform tasks such as copying data served up a device to user/kernel buffers, since such tasks can always be delayed. Third, devices that have real-time constraints on when their data is handled should be given higher priority than other devices. Also, devices that do not have any form of buffering for its data would have to be assigned higher priority since the data could be available only for a short period of time. 13.2 What are the advantages and disadvantages of supporting memory-mapped I/O to device-control registers? Answer: The advantage of supporting memory-mapped I/O to device-control registers is that it eliminates the need for special I/O instructions from the instruction set and therefore also does not require the enforcement of protection rules that prevent user programs from executing these I/O instructions. The disadvantage is that the resulting flexibility needs to be handled with care; the memory translation units need to ensure that the memory addresses associated with the device control registers are not accessible by user programs in order to ensure protection.

8 – Memory Systems

Chapter 8 covers memory system architecture and describes how computers communicate with peripheral devices such as keyboards and printers.

4 – Hardware Description Languages

Chapter 4 describes hardware description languages (HDLs). HDLs are related to conventional programming languages but are used to simulate and build hardware rather than software. Most digital systems today are designed with HDLs. SystemVerilog and VHDL are the two prevalent languages, and they are covered side-by-side in this book.

Microarchitecture: With contributions from Matthew Watkins

Chapter 7 covers microarchitecture, the arrangement of digital building blocks, such as adders and registers, needed to construct a processor. This chapter shows how to build a MIPS processor. It covers three microarchitectures illustrating different trade-offs of performance and cost. Processor performance has increased exponentially, requiring ever more sophisticated memory systems to feed the insatiable demand for data.

5 – Digital Building Blocks

Chapter 5 covers other combinational and sequential building blocks such as adders, multipliers, and memories.

Chapter 6 – Architecture

Publisher Summary To command a computer, one must speak its language. Computer architecture defines how to command a processor. Many different computer architectures are in widespread commercial use today. Microprocessor without Interlocked Pipeline Stages (MIPS) is a 32-bit architecture because it operates on 32-bit data. The MIPS architecture has 32 general-purpose registers. In principle, almost any register can be used for any purpose. However, by convention, certain registers are reserved for certain purposes for ease of programming and so that procedures written by different programmers can communicate easily. This chapter discusses the most commonly used MIPS instructions. The power of defining computer architecture is that a program written for any given architecture can run on many different implementations of that architecture.