Saroj Pathak

A 23 ns 256 K EPROM with double-layer metal and address transition detection

A 256 K EPROM (electrically programmable read-only memory) is described in which 23-ns access time was achieved by a combination of advanced CMOS processing, double-layer metal (DLM), differential sensing, address transition detection (ATD), and a ground-switched decoding scheme. DLM is used to strap wordlines in the array and bus signals in the periphery. Performance is obtained by reducing bit line length to 256 cells, with 2048 cells per word line. This results in a 70.5-mil*229.8-mil array with an efficiency of 41.2%. Die size is 116 mil*339 mil. Short bit lines result in a total column and Y-select capacitance of 1.3 pF. Word line RC delay is only 0.8 ns. DLM saves 7.3 ns over an optimized silicide design using two word line drivers. The 0.8- mu m CMOS DLM EPROM technology yields a typical unloaded ring oscillator gate delay of 115 ps. Lightly doped drain (LLD) is used on both NMOS and PMOS devices for reliability and performance. Ti/Al metalization improves metal reliability. A composite interpoly dielectric is used for improved FAMOS (floating-gate avalanche-injection MOS) reliability.<<ETX>>

A 25ns 16K CMOS PROM using a 4-transistor cell

A 25ns, 250mW, 2K×8 PROM using 1.2μ N-well CMOS technology will be described. Speed and programmability have been optimized by separating read and write transistors in a 4-transistor differential cell. A substrate bias generator raises the latchup immunity to over 200mA.

A 25-ns 16K CMOS PROM using a four-transistor cell and differential design techniques

A 25-ns, 250-mW, 2K/spl times/8 PROM using a 1.2-/spl mu/m n-well CMOS technology is described. Speed and programmability are optimized by separating the READ and WRITE transistor functions in a four-transistor differential cell and using differential design techniques. For the first time, a substrate bias generator is used in an EPROM technology to improve speed and raise latch-up immunity to over 200 mA.