Satheesh Kuppurao

Epitaxial Si punch-through based selector for bipolar RRAM

Resistive RAM is a very promising candidate for high density non-volatile memory. Although bipolar operation has been shown to work at lower current (essential for low power, mobile computing) [1], a suitable selector device that delivers high current density and high on/off current ratio is challenging [2–4]. We demonstrate a 4F2 bipolar selector device based on the punch-through mechanism. An npn vertical junction device fabricated using in-situ doped epitaxial silicon is presented. Superior on-current density (Jon=1MA/cm2) and high on-off current ratio (Ion/Ioff) of 300–5000 is experimentally demonstrated. TCAD simulations based performance, variability and scalability are presented.

The high growth rate of epitaxial silicon-carbon alloys by using chemical vapour deposition and neopentasilane

The growth of epitaxy of silicon–carbon (Si1−yCy) alloy layers on (1 0 0) silicon substrates by chemical vapour deposition (CVD) with a novel precursor, neopentasilane, as the silicon source gas and methylsilane as the carbon source is reported. High quality Si1−yCy alloy layers at growth rates of 18 nm min −1 and 13 nm min −1 for fully substitutional carbon levels of 1.8% and 2.1%, respectively, were achieved. The highest substitutional carbon level achieved was 2.6% (strained perpendicular lattice constant of 5.347 u A) as determined by x-ray diffraction. (Some figures in this article are in colour only in the electronic version)

Fabrication of

Segmented-channel Si₁_-_xGe_x/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si₁_-_xGe_x/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si₁_-_xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher <i>I</i>_ON for <i>I</i>_OFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}

Epitaxially grown Silicon Carbon (Si:C) in recessed junction regions has been shown to induce tensile stress in the nMOS channel and thereby enhance the transistor performance. In addition to the stress induced in the channel, this technology also needs to achieve low resistivity junctions for widespread use. This work discusses epitaxially grown heavily doped Si/ Si:C layers which can be used in nMOS junctions and can address both these requirements. Si:C epitaxial layers are shown to have phosphorus concentrations as high as 1.25 X 10^21 cm^-3 with resistivities as low as 0.3 mOhm.cm. Applications of these layers can range from Si:P cap layers for low series resistance to Si:PC layers for inducing stress in the nMOS channel.

pMOSFETs Using Corrugated Substrates for Improved

INTRODUCTION It is understood that a uniaxial tensile stress along a channel of transistor enhances electron mobility and drive current of NMOS transistors. Typically, a tensile stress-enhanced silicon nitride layer is used to strain the channel [1]. For even further enhancement of transistor drive current, a use of silicon carbon alloy (Si:C) in recessed source/drain (S/D) area has been considered. Alloying Si with C decreases lattice parameters when carbon atoms occupy substitutional sites of Si lattices. Very recently, it has been reported that a use of Si:C epitaxy in recessed S/D generates tensile strain in the channel of NMOS transistor and consequently increases transistor drive current [2]. The Si:C recessed S/D technology has two major challenges in preparing an epitaxy solution: One is how to incorporate carbon atoms into substitutional sites. As the solid solubility of substitutional carbon in silicon is only ~10 cm, carbon atoms at concentrations higher than this easily incorporate into interstitial sites or precipitate as β-SiC, resulting in no strain in the epilayer. Therefore, in order to achieve high substitutional carbon concentration (≥ 1%) with minimizing interstitial carbon concentration, non-equilibrium epitaxial growth conditions such as low temperature (≤ 600 C) are required [3]. The other is to obtain selectivity and reasonable growth rate of selective Si:C epitaxy process with maintaining high substitutional carbons. We have developed selective Si:C epitaxy processes with 1% or higher substitutional carbon concentration and will discuss characteristics of the epitaxy grown on recessed area of patterned wafers.

I_{\rm ON}

The worlds first GeSn p-FinFETs formed on a novel GeSn-on-insulator (GeSnOI) substrate is reported, with channel lengths L<inf>ch</inf> down to 50 nm and fin width W<inf>Fin</inf> down to 20 nm. In comparison with other reported GeSn p-FETs, record low S of 79 mV/decade, record high G<inf>m, int</inf>, of 807 μS/um (VDs of −0.5 V), and the highest G<inf>m, int</inf>/S<inf>sat</inf>, were achieved. The highest high-field hole mobility of 208 cm2/Vs (at inversion carrier density of 8×10⁻² cm⁻²) for GeSn p-FETs with CVD grown GeSn channel was also obtained.

and Reduced Layout-Width Dependence

Segmented-channel Si_1-xGe_x/Si pMOSFETs are fabricated using a conventional process, starting with a corrugated Si_1-xGe_x/Si substrate. As compared with control devices fabricated using the same process but starting with a non-corrugated Si_1-xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher I_ON for I_OFF=10 nA per μm layout width) due to enhanced hole mobility, and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

Heavily Phosphorus Doped Silicon Junctions for nMOS Applications

INTRODUCTION Selective epitaxy has gained increasing momentum in advanced high-performance logic as well as volatile and nonvolatile memory device fabrication. The advantages of this technique range from the well documented application of strained SiGe epitaxial films used to increase hole mobility and performance in pFET devices to intrinsic Si epitaxial layers used to prevent short channel effects in memory devices (DRAM). Other applications call upon the time tested strengths of epitaxy in ensuring abrupt, activated doped layers or junctions without the defectivity associated with implanted profiles.

Application of Selective Si:C Epitaxy For Recessed Source/Drain Technology

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on <110> channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs

Pseudomorphic Ge_0.91Sn_0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge_0.91Sn_0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on <;110> channel direction is observed using external transverse uniaxial tensile strain (~0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I_on/I_off ratio, and strain-enhanced mobility are obtained in this work.