Satoru Machida

Investigation of correlation between device structures and switching losses of IGBTs

This study investigated the correlation between the device structures and the switching power dissipation by using an index, the ratio of feedback capacitance to input capacitance. We point out that a wide-cell-pitch and an injection enhanced structure have inherently higher switching power dissipation under the fitted dV/dt and dI/dt condition because of their large index.

Approaching the limit of switching loss reduction in Si-IGBTs

This paper reports on the reduction limit of switching loss in Si-IGBTs without increasing the on-state voltage. We focused on surge decrease and turn-off loss saturation with small gate resistance. It became clear that the surge decrease derives from a dynamic avalanche adjacent to the trench bottom and leads to the turn-off loss saturation. This avalanche phenomenon is suppressed by the reduction of the electric field and positive space charge near the trench bottom. A 20 % improvement in the trade-off relation with small gate resistance was realized by the suppression of the dynamic avalanche, which is close to the turn-off loss reduction limit.

Effects of Trap Levels on Reverse Recovery Surge of Silicon Power Diode

In this paper, we report on the effects of trap energy levels on the reverse recovery surge, for the first time. The different current and temperature dependences of the reverse recovery surge with shallow and deep trap energy levels were measured. Results of simulations of current and temperature dependences of the reverse recovery surge with different trap energy levels were similar to measurement results. Through numerical and theoretical analyses based on the Shockley–Read–Hall (SRH) model, it was confirmed that variations in recombination rate due to different trap energy levels affect the current and temperature dependences of the reverse recovery surge. We found that in order to achieve a soft recovery in the design of silicon power diodes, the trap energy levels play a crucial role along with the carrier lifetime profile.

Theoretical analysis of forward voltage and reverse recovery charge of silicon p–i–n diodes

Silicon p–i–n diodes have attracted considerable attention for their use as many applications. In the light of reducing total power loss, the forward voltage Vf and the reverse recovery charge Qr of silicon p–i–n power diodes are controlled by using two approaches based on control of either carrier lifetime or carrier injection efficiency. In this study, we investigate the effect of the two approaches on the relationship between Vf and Qr for a Si p–i–n diode rated at 200 A/1200 V via theoretical analyses. The magnitude of Vf for a given Qr value depends on rate of current density decreasing dj/dt. In the case of large values of dj/dt, carrier injection control can lead to decrease in Vf and Qr to a greater extent. In contrast, at small values of dj/dt, carrier lifetime control can provide a greater decrease in Vf and Qr.

Simulation of turn-off oscillation suppression in silicon insulated gate bipolar transistors

The mechanism of the suppression of turn-off oscillation by a neutral region remaining in a silicon insulated gate bipolar transistor was investigated. From the AC analysis of the neutral region using device simulation, we found that the turn-off oscillation is not damped by the resistance of the neutral region. We proposed a model in which a current source (tail current) connected between the collector and emitter terminals in series with the capacitance can suppress the turn-off oscillation. The results of circuit simulation based on this model, it became clear that the tail current acts as a damping resistance upon the LC resonance circuit. We concluded that the turn-off oscillation is suppressed by the tail current caused by the remaining neutral region.

Minimization of reverse recovery charge and forward voltage of silicon p–i–n diodes

The forward voltage and reverse recovery charge of silicon p–i–n diodes are controlled on the basis of carrier lifetime or carrier injection efficiency to reduce power loss. In this study, the ideal carrier lifetime for minimizing power loss is calculated by theoretical analysis. The ideal carrier lifetime depends on the current density, forward voltage, and trap energy level in the intrinsic layer. A decrease in the current density leads to an increase in the ideal lifetime. In addition, a shallow trap level has similar current dependence on ideal lifetime. Using the appropriate lifetime is important for designing a p–i–n diode, and a shallow trap level can achieve greater ideal current density dependency.

Turn-on analysis of silicon insulated gate bipolar transistors with emitter trenches

In this study, we analyzed the turn-on of silicon insulated gate bipolar transistors (IGBTs) with an emitter trench. The tail of collector-to-emitter voltage during turn-on fluctuated when an emitter trench was inserted. Interestingly, the gate-to-collector capacitance of IGBTs with an emitter trench was lower than that without an emitter trench. The internal hole current distribution at the time of the tail of collector-to-emitter voltage was investigated by device simulation. The hole current was diverted, passing adjacent to the emitter trench. It was clarified that the fluctuation in the tail of collector-to-emitter voltage originates from a decrease in PNP transistor gain associated with this change of the hole current path. We demonstrated that this fluctuation in the tail of collector-to-emitter voltage can be suppressed by connecting the emitter trench to a gate electrode.

Suppression of reverse recovery surge voltage of silicon power diode by adjusting trap energy levels through local lifetime control

To suppress the reverse recovery surge voltage of silicon power diodes, the effects of adjusting trap energy levels through local lifetime control were investigated by device simulation and theoretical analysis of the Shockley–Read–Hall (SRH) model. In general, local lifetime control techniques localize carrier traps at the anode side of a diode and optimize the carrier lifetime profile to suppress surge voltage. However, the suppression effect of a certain localized trap density distribution on surge voltage varies with a change in trap energy level, even if the trap density distribution is the same. It became clear that deep trap energy levels suppress surge voltage more than shallow trap energy levels at 1000 A/cm2 or less. Thus, deep trap energy levels such as Et − Ei = 0.0–0.2 eV are favorable for suppressing surge voltage in almost all power devices.

Suppression of Reverse Recovery Surge Voltage of Silicon Power Diode by Adjusting Trap Energy Levels through Local Lifetime Control

To suppress reverse recovery surge voltage of silicon power diodes, effects of trap energy levels adjusted through local lifetime control were investigated. It was found that a deep trap energy level reduced surge voltage at 1000A/cm or less current density regions.