Satoshi Horiike

A design method of systolic arrays under the constraint of the number of the processors

This paper proposes a systemtic method to design systolic arrays under the constraint of the number of the processors. Our basic approach is to partition the large systolic array into the smaller number of groups, whose number is coincident with the number of processors to be used. We give the mathematical method to make at most one processor execute computation in each group. Then, each group can be replaced by one processor to satisfy the constraint of the number of the processors.

The Time/Place/Object model for tracking and history management in manufacturing line control

Tracking and production history management for manufacturing lines requires the ability to retrieve traced-back production performance data from raw materials to final products. Requirements are not so simple. At first, manufactured objects are split into or combined with other objects. Since traditional temporal models concentrate on time-varying or time-series objects, the change of the unit of object management cannot be handled. Secondly, not only object branching and merging but also object dividing and accumulating need to be represented. Conventional workflow models focus on only branching and merging, because of the characteristics of the workflow domain. Thirdly, production histories need to be retrieved in different perspectives according to the purpose of the retrieved data. However, the view of the temporal models is focusing on only the time dimension, while the view of workflow history is only a projection from entire history. We propose the Time/Place/Object model to satisfy the requirements in manufacturing line management and describe the structure and the behavior of a manufacturing line. The model provides the definite categories of five process primitives, three object forms, four invocation logics of ECA rules, and three views of production history. We have developed a family of middleware based on the model and applied it to a tracking system for a steel mill plant.

Real-time communication in plant-monitoring/controlling systems with ATM networks

We propose a method for a schedulability check in ATM networks which provide fixed prioritized virtual connections. Our method does not need any run-time scheduling other than fixed priority scheduling at each output link of all switch nodes and traffic shaping at each output link of cell terminal nodes in a network. Rate monotonic analysis assumes a critical instance in which all tasks arrive at the same time. We, however, can obtain information on the times when messages arrive at switch nodes in a network. Using such information, our method can check the schedulability of a set of channels more exactly than the method assuming a critical instance.

A reusable object model for integrating design phases of plant systems engineering

In recent years, cost reduction is strongly required for most system development. In plant systems engineering, integration of information which is commonly utilized in some design phases from the plant design level to the programming level should be considered. In this paper, we propose a reusable object model for plant systems engineering, realizing the integration of information through design phases. We propose a machine template as a unit of reusable objects. We also have developed an engineering environment tool based on the reusable object model and applied it to building several systems. As a result, the system development time could be decreased to 2/3, as compared with the past system of the same scale.

A task mapping method for a hypercube

This paper presents a new algorithm for task mapping onto a hypercube. The structure of parallel programs can be expressed by a task graph. With this graph, the algorithm generates a mapping that reduces communications costs considerably. When the target computer is an n-dimensional cube (n-cube), the algorithm is composed of n stages. It starts with an initial state in which the tasks are mapped onto 2+ 0-cubes. At each stage k, the task graph is mapped onto 2n-kk-cubes. The mapping onto k-cube can be accomplished by combining two (k -1)-cubes.

Systematic design of systolic arrays using mapping algorithm

A method to derive the architecture of systolic arrays is discussed. The focus is on the mapping algorithm proposed by D.I. Moldovan (Proc. IEEE, vol.71, no.1, p.113-20, 1983). The algorithm is based on the idea of transforming the indices of the do-loop structured program into time and space using a matrix. It is shown that many requirements which appear in the practical design of the systolic array can be expressed by the mathematical constraints of the matrix. These constraints allow a more systematic determination of the transformation matrix.<<ETX>>

Expanding small example into large scale real-time control system

This paper proposes the example expansion which supports control system development. In the example expansion, real-time system engineers familiar with programming for real-time computing develop a small example for maintaining the timing consistency. Since the example is small, its development is easy. The example is expanded according to requirements specified by control engineers who are unfamiliar with real-time computing but have expertise in the regulation of a specific plant. Since formal rules and tools expand the example, a mechanism for maintaining the timing consistency is correctly transferred to a target system. The example expansion allows the two kinds of engineers to concentrate on their own work. A control system for a steel mill plant has been developed using this method, and the system has been developed 2.7 times faster than the time taken with a conventional method.