Satoshi Shigematsu

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFETs in a single LSI. The low-threshold voltage MOSFETs enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFETs suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSIs. To demonstrate MTCMOSs effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving high-speed, ultralow-power large-scale integrators (LSIs) for battery-driven portable equipment. The balloon circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology. Moreover, this scheme is effective for high speed and low-power operation in quarter-micrometer and finer devices.

A single-chip fingerprint sensor and identifier

A chip architecture that integrates a fingerprint sensor and an identifier in a single chip is proposed. The fingerprint identifier is formed by an array of pixels, and each pixel contains a sensing element and a processing element. The sensing element senses capacitances formed by a finger surface to capture a fingerprint image. An identification is performed by the pixel-parallel processing of the pixels. The sensing element is built above the processing element in each pixel. The chip architecture realizes a wide-area sensor without a large increase of chip size and ensures high sensor sensitivity while maintaining a high image density. The sensing element is covered with a hard film to prevent physical and chemical degradation and surrounded by a ground wall to shield it. The wall is also exposed on the chip surface to protect against damage by electrostatic discharges from the finger contacting the chip. A 15/spl times/15 mm/sup 2/ single-chip fingerprint sensor/identifier LSI was fabricated using 0.5-/spl mu/m standard CMOS with the sensor process. The sensor area is 10.1/spl times/13.5 mm/sup 2/. The sensing and identification time is 102 ms with power consumption of 8.8 mW at 3.3 V. Five hundred tests confirmed a stranger-rejection rate of the chip of more than 99% and a user-rejection rate of less than 1%.

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application

A 1-V power supply low-power and high-speed 16-b fixed-point digital signal processor using a 0.5-/spl mu/m process has been developed for mobile phone applications. A 1-V multithreshold-voltage CMOS (MTCMOS) technology that uses both high-threshold-voltage and low-threshold-voltage transistors is one key to attaining low power consumption, keeping processing throughput high. A maximum operating frequency of 13.2 MHz and an energy consumption of 2.2 mW/MHz were achieved at 1 V. The second key to low-power operation is a power management scheme that uses a secondary embedded microprocessor. This proposed scheme minimizes the standby power in the waiting state by effectively controlling the sleep mode in the MTCMOS design. We confirmed that the standby leakage current was reduced three orders of magnitude and that the energy consumed in the waiting state was less than 1/10 of that consumed by conventional CMOS circuits with lowered supply voltage and threshold voltage but without power management.

A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application

A low-power digital signal processor (DSP) is the key component for battery-driven mobile phone equipment since a vast amount of data needs to be processed for multimedia use. Reduced supply voltage is a direct approach to power reduction. This 1 V DSPLSI with 26 MOPS and 1.1 mW/MOPS performance adopts a multi-threshold-voltage CMOS (MTCMOS) technique. A small embedded power-management processor decreases power during waiting periods.

A 1-V high-speed MTCMOS circuit scheme for power-down applications

A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.

A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors

Novel capacitive fingerprint sensor techniques are described. We propose a novel sensor cell architecture to obtain high sensitivity, wide output dynamic range, and contrast adjustment. For the architecture, three circuit techniques were developed. A sensing circuit with a differential charge-transfer amplifier enhances sensitivity while it suppresses the influence of the parasitic capacitance of the sensor plate. A wide output dynamic range, which is needed for high-resolution analog-to-digital (A/D) conversion, is achieved by transforming the sensed voltage to a time-variant signal. Finally, the sensing circuit includes an automatic contrast enhancement scheme that uses a variable-threshold Schmitt trigger circuit to distinguish the ridges and valleys of a fingerprint well. The characteristics of a test chip using the 0.5-/spl mu/m CMOS process show a high sensitivity to less than 80 fF as the detected signal, while the variation of the output signal is suppressed to less than 3% at /spl plusmn/20% variation of the parasitic capacitance. The dynamic range of the time-variant signal is 70 /spl mu/s, which is wide enough for A/D conversion. The automatic contrast enhancement scheme widens the time-variant signal 100 /spl mu/s more. A single-chip fingerprint sensor/identifier LSI using the proposed sensing circuit scheme confirms the schemes effectiveness.

Design method of MTCMOS power switch for low-voltage high-speed LSIs

The design of the power switch which turns on and off the power supply to the logic gates is essential to low-voltage high-speed circuit techniques such as multi-threshold voltage CMOS (MTCMOS). This is because this switch influences the speed, area, and power of a low-voltage LSI. This paper describes the influences of the power switch on the circuit performance in detail, and proposes a systematic method for designing a power switch which takes them into consideration for the first time. The main feature of this method, called the average-current method, is the use of the average current consumed in an LSI to determine the power-switch size. This makes it easy for designers to determine the minimum size of the power-switch needed to satisfy the required speed, which results in minimizing the area penalty and the standby power. Useful analytical formula and the practical determination flow are also described. Measurement of an actual 0.25 /spl mu/m MTCMOS/SIMOX 290-Kgate LSI operating at 1 V confirmed the effectiveness of this method. This method estimated well the required power-switch width, and as a result it reduced the area penalty and standby current by about 80% compared to the conventional design scheme.

A 0.5-V MTCMOS/SIMOX logic gate

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-/spl mu/m MTCMOS/SIMOX technology.

A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate

Multi-threshold CMOS (MTCMOS) circuit technology combining low-Vth CMOS logic gates and high-Vth MOSFETs is suitable for 1 V LSIs for battery-operated portable equipment. Improvements in MTCMOS device technology promise to lead to higher operating frequencies. However, higher frequencies will increase power consumption even if the supply voltage is 1 V. To reduce the power consumption, it is necessary to lower the supply voltage below 1 V, without sacrificing speed. A circuit consisting of depletion-mode MOSFETs operates with 200 mV supply. However, it cannot be applied to an LSI with more than 1 k gates because active-mode leakage current is too large. In addition, the circuit needs backgate bias, which is much larger than the supply voltage, to increase the threshold voltage and to reduce the leakage current in the sleep mode. To generate the large back-gate bias, multiple supply voltages or a boost circuit are required. The proposed low supply-voltage MTCMOS circuit with SIMOX technology uses enhancement-mode MOSFFTs and contains no boost circuit. High-speed operation of this SIMOX-MTCMOS circuit at 0.5 V supply is obtained by use of low-Vth CMOS logic gates consisting of fully-depleted body-floating MOSFETs.