Satyabrata Dash

Analog Circuit Optimization Based on Hybrid Particle Swarm Optimization

With growing Electronic Design Automation (EDA) industry, automated analog circuit design is now a feasible solution for the demand to exploit a span of nonlinear circuit behaviours from devices to circuits with the flexibility to optimize numerous competing continuous-valued performance specifications. In order to meet desired specifications, state-of-art EDA tools are employed which depend upon more efficient and effective optimization techniques to suffice the cost of designing complex analog systems. In this paper, a hybrid metaheuristic based on PSO and SA is presented to design one of the most prominent design specifications, i.e. gains of a two-stage CMOS operational amplifier circuit and a simple operational transconductance amplifier circuit subject to a variety of design conditions and constraints. Here convergence of PSO is improved by advancing through local solutions using SA to achieve quality global optimum solution. Experimental results are compared with other standard optimization techniques to show performance of proposed hybrid metaheuristic in terms of optimization quality and robustness.

CMOS analog circuit optimization via river formation dynamics

As silicon process geometry is reduced in scale with growing Electronic Design Automation (EDA) industry, the underlying circuitry on a chip has become more complex. The cost of designing such complex systems drives towards the path of employing automation in the field of analog circuit design. In this paper, a heuristic based on river formation dynamics (RFD) is presented to design analog circuits with user-defined specifications. Here search strategy of RFD scheme is employed to advance through stringent design requirements to evaluate an optimum solution for two-stage CMOS operational amplifier circuit. Experimental results show competent performance of RFD scheme in terms of quality of solution when compared with standard optimization techniques.

Applying River Formation Dynamics to Analyze VLSI Power Grid Networks

One of the major concerns in todays CMOS VLSI design is reliable on-chip power delivery. As semiconductor technology continues to scale down day-by-day, different process variabilities in silicon keep on manifest themselves affecting the chip performance. One of the critical process induced variations come from worst-case voltage fluctuations (hotspots) across power rails of a chip. These fluctuations have become more significant with increase in size of power grid networks. Thus, it is necessary to locate the hotspots accurately throughout the power grid network for efficient design verification by using suitable computing environment and a correct methodology. In this paper, a heuristic based on parallel river formation dynamics (RFD) scheme is proposed to analyze large power grid networks on graphics processing unit (GPU). Here the concept of RFD to pursue a path using gradient orientation is applied to identify hotspots across the power grid network. Experimental results show that RFD accelerates the analysis by efficiently exploiting the structure of power grid network on GPU to achieve remarkable speedups with acceptable accuracy loss.

Power grid analysis on parallel computing platforms

Due to extremely large size of power grid networks, the realistic simulation of VLSI power distribution network (power grid analysis) is computationally intensive both in terms of runtime and memory. The ongoing trends in technology scaling imply to design fast and power efficient circuits. With smaller feature sizes and variability in silicon, it has become a challenging task to design and analyze a reliable power distribution network inside a chip for correct logical functioning of an electronic circuit. In order to analyze a power grid network accurately and efficiently, a suitable computing environment and a correct technique need to be adopted. This work presents a parallel technique based on random walk algorithm using parallel computing environments like Intel Xeon Phi and Graphics Processing Unit. The proposed method has shown speedup of 55 and 67 folds as compared to its sequential version while analyzing a power grid network having 25 million nodes on Intel Xeon Phi co-processor and Graphics Processing Unit (GPU) respectively.

A method of analog circuit optimization using adjoint sensitivity analysis

Analog circuit designing is an important aspect of VLSI chip design process. For the designing of analog circuits, electronic design automation tools need to be equipped with state-of-the-art efficient circuit analysis and optimization techniques. In this paper, a novel approach to optimize analog circuits (for gain, bandwidth and slew rate) is proposed using adjoint circuit analysis method. In this method an adjoint network of the original electrical (or electronic) circuit is constructed by using linearized circuit of the original electrical network in which MOS transistors are replaced by their small signal model. The objective function need to be analyzed for the optimization of analog circuit is evaluated using linearized circuit and its adjoint network (circuit) along with steepest descent method to find the next set of design parameters to optimize circuit in the design space. Barzilai and Borwein method is used to find the direction of design parameter vector during circuit optimization process. In this paper a basic cascode amplifier circuit has been designed at 180nm technology to prove the correctness of proposed method. To prove the effectiveness of the proposed approach, a two-stage operational amplifier circuit is also designed for gain optimization subject to a variety of design conditions and constraints. The solution of these circuits, designed with the optimized parameters calculated using our proposed method, matches with the solution of cascode amplifier and two-stage operational amplifier circuits designed using Mentor Graphics tool Pyxis (Eldo).

Multiobjective analog/RF circuit sizing using an improved brain storm optimization algorithm

AbstractThis paper presents a multiobjective analog/RF circuit sizing tool using an improved brain storm optimization (IMBSO) algorithm with the purpose of analyzing the tradeoffs between competing performance specifications of analog/RF circuit block. A number of improvements are incorporated into IMBSO algorithm at different steps. At first, the clustering step of IMBSO algorithm is augmented with k-means

Markov Chain Model Using Lévy Flight for VLSI Power Grid Analysis

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PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution

++ seeding technique to select the initial cluster centroids while clustering using k-means clustering technique. As a second improvement, the proposed IMBSO algorithm makes use of random probabilistic decision-making of river formation dynamics scheme to select optimal cluster centroids during population generation step. As a third improvement, an adaptive mutation operator is incorporated inside the IMBSO algorithm to generate new population. Finally, two separate constraint handling techniques are employed to handle both boundary and functional constraints during analog/RF circuit optimization. The performance of the proposed IMBSO algorithm is demonstrated in finding optimal Pareto fronts among different performance specifications of a two-stage operational amplifier circuit, a folded cascode amplifier circuit and a low noise amplifier circuit.