Sau-Gee Chen

A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is 0.93 mm2, and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation.

Energy-Bandwidth Efficiency Tradeoff in MIMO Multi-Hop Wireless Networks

This paper considers a MIMO multi-hop network and analyzes the relationship between its energy consumption and bandwidth efficiency. Its minimum energy consumption is formulated as an optimization problem. By taking both transmit antennas (TAs) and receive antennas (RAs) into consideration, the energy-bandwidth efficiency tradeoff in the networks is investigated. Moreover, the minimum energy of an equally-spaced relaying strategy is investigated for various numbers of antennas. In addition, the minimum energy over all possible antenna pairs is derived. Finally, the effect of the number of hops on the energy-bandwidth efficiency tradeoff is considered. For a fixed antenna pair, the minimum energy over all possible rates and hop numbers are obtained. Generally, the routes with more hops minimize the energy consumption in the low effective rate region. On the other hand, in the high effective rate region, the routes with fewer hops minimize the energy consumption.

Efficient channel estimation based on discrete cosine transform

Channel impairment caused by multipath reflections can deeply degrade the transmission efficiency in wireless communication systems. Based on the property of the channel frequency response and the concept of interpolation, a DCT-based pilot-aided channel estimator for orthogonal frequency division multiplexing is proposed. This approach can mitigate the aliasing effect in the DFT-based channel estimator when there is non-sample-spaced path delay. Compared with a DFT-based estimator, the DCT-based estimator significantly improves the performance with a comparable complexity. In addition, a noise reduction scheme is introduced and combined with the estimator. In implementation, the DCT-based estimator has the advantages of utilizing mature fast DCT algorithms and compatible FFT algorithms, which is favorable to other matrix-based channel estimation methods.

A Blind Synchronizer for OFDM Systems Based on SINR Maximization in Multipath Fading Channels

This paper presents a blind synchronizer for orthogonal frequency-division multiplexing (OFDM) systems based on signal-to-interference-and-noise ratio (SINR) maximization. Due to the incurred losses from intersymbol interference (ISI) and intercarrier interference (ICI) introduced by synchronization errors, the SINR of the received data drastically drops. By taking advantage of this characteristic, both the symbol time and carrier frequency offsets are intuitively estimated by maximizing the SINR metric. For the SINR metric, two blind SINR estimations are investigated. The estimations do not need prior knowledge of the channel profiles and transmitted data. As such, the proposed maximum SINR (MSINR) synchronization algorithm is nondata aided so that the transmission efficiency can be improved. Moreover, to reduce the computational complexity, the early-late gate technique is proposed for the implementation of the synchronizer. Simulation results exhibit better performance for the MSINR algorithm than conventional techniques in multipath fading channels.

High quality and low complexity pitch modification of acoustic signals

A high-quality and low-complexity algorithm for pitch modification of acoustic signals is proposed. It is high quality, because time-domain waveform shape and phase synchrony of a synthesized signal closely resemble that of its original signal. Low complexity is attained by performing the algorithm entirely in time domain with fast algorithm, and without resorting to complicated frequency domain analysis and synthesis. The time domain synthesis mostly consists of fast algorithms of finding minimum absolute error (MAE) and a cross fading operation for high correlation gain and phase synchrony. The MAE-based algorithm is shown to yield smaller complexity, and better performance, than other well-known correlation cost functions. Pitch modification is performed by selecting and synthesizing apposite frames from original input signals in a way such that the original waveform shape and phase synchrony are preserved. Subjective tests showed a comparable performance to that of the best known algorithms, but at much reduced complexity.

IEEE 1588 clock synchronization using dual slave clocks in a slave

IEEE 1588 is a standard used in the synchronization of independent clocks that run on separate nodes of a distributed measurement and control system. This work presents a method that employs dual slave clocks in a slave to measure the link propagation delay, clock skew and offset. By accurately deriving these parameters, the proposed approach can reduce the deviation from the master clock to several orders of magnitude better than the required specification. The proposed technique fully conforms to the IEEE 1588, and can be used in the environments of symmetric and asymmetric communication links, such as xDSL.

Efficient CORDIC Designs for Multi-Mode OFDM FFT

In this paper, we propose a new CORDIC algorithm and architectures which can generate close-to-optimum rotation sequences easily with small lookup table sizes. This new design is particularly suitable for the applications of adjustable-length FFT. In all, the required number of shift-and-add operations for micro-rotations and scale-factor compensations is only n/2, where n is the output precision. For design verification, we synthesized both serial and pipelined architectures, by using synopsys design compiler based on UMC 0.18 mum, 1P6M CMOS technology. The synthesized 16-bit pipelined FFT PE runs at 222 MHz, with a total gate count of 89263 and a low-power consumption of 26.75 mW. It meets the FFT speed requirements of most OFDM-based communication systems, including DAB, DVB, 802.16 and VDSL. Compared with a conventional multiplier-based FFT PE and the existing CORDIC-based FFT PEs, the proposed designs has better performances in terms of area, speed and power consumption

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

Reduction of Doppler-induced ICI by interference prediction

Although wireless OFDM systems are robust against frequency-selective fading and ISI effects, their relatively long symbol lengths are vulnerable to time-selective fading and ICI (intercarrier interference) effects in mobile environments due to Doppler spread. However, commonly, a time-selective fading channel is linearly time-varying from symbol to symbol for existing wireless communication systems and vehicle speed limits. The linear property greatly reduces channel parameters. Based on this condition, we propose an ICI-reduction method. The ICI-reduction method first solves the linear channel parameters of each path, and then combines with a decision-feedback method to predict the ICI values from the estimated channel information, followed by the subtraction of the ICI components. Further, the proposed algorithm adopts an iterative ICI refinement technique to enhance the ICI prediction accuracy. The simulation results show that the new method can effectively reduce the ICI and error floor of the symbol error rate. The proposed algorithm is further simplified. The simplified version still maintains almost the same performance as before, with a much reduced complexity.

On the Analysis of Combined Synchronization Error Effects in OFDM Systems

This work analyzes combined effects of major syn- chronization errors, including the symbol time offset (STO), car- rier frequency offset (CFO) and sampling clock frequency offset (SCFO) of orthogonal frequency-division multiplexing (OFDM) systems. Such errors degrade the performance of an OFDM re- ceiver by introducing inter-carrier interference (ICI) and in- ter-symbol interference (ISI) into the systems. Traditionally, de- signing an OFDM receiver needs plenty of Monte Carlo simula- tions because the synchronization errors are simultaneously in- evitable in practical environments. Therefore, we formulate the theoretical signal-to-interference-and-noise ratio (SINR) to assist the design of OFDM receivers. By knowing the required SINR of specific application, all combinations of allowable errors can be derived. Then, cost-effective algorithms could be easily designed.