Savithra Eratne

A quasi-power-gated low-leakage stable SRAM cell

Leakage power dissipation and stability continues to be a major concern in deep-submicron SRAM cell design. In this paper, a quasi-power-gating approach that reduces the leakage power dissipation in an SRAM cell while maintaining stability is proposed. As compared to a standard 6-transistor SRAM, it consists of four additional NMOS transistors. In the active mode, the cell is activated by enabling two NMOS transistors in the pull-down path of the inverter. In the idle mode, a quasi-power-gating scheme is employed to reduce leakage by utilizing stack effect. It was found that this cell resulted in about 39.54 percent and 30.5 percent leakage power savings at a supply voltage value of 1V and 300mV respectively. A stability increase was also observed when compared to the standard non-power-gated 6-transistor SRAM cell.

Fast Predictive Wavelet Transform for lossless image compression

This paper presents a new, simple, lossless image transform with high speed, high energy compaction and low power for digital image compression. The proposed transform follows the Haar Wavelet Transform (HWT) using the hierarchical structure, with low complexity, prediction based method of computation of the elements instead of the traditional waveforms used with Haar Transform. Energy compaction rate of this Predictive Wavelet Transform is 28% better than HWT after 75% reduction in computations.

Leakage control in full adders with selectively stacked inverters

Technology scaling beyond the 65nm regime has resulted in leakage power consumption emerging as a major design constraint. Several methods aiming at mitigating leakage power have been studied and tested. These include power-rail gating, input vector control, transistor body biasing, transistor stacking, etc. This paper extends the idea of transistor stacking but limiting it to the inverters in the given logic circuit or cell in order to obtain leakage savings. Stacking of inverters is effective in leakage current reduction during both the active and standby modes of the circuit. Stacking also has the advantage of not requiring any additional control circuitry. We examine the leakage power and delay variations for this approach and compare it with the method of power-rail gating. The results indicate that selective stacking of inverters can yield considerable leakage savings without causing significant delay penalties. Therefore it is suitable for cells such as full adders which are in the critical path of complex logic modules such as the microprocessor.

Leakage current control of nano-scale full adder cells using input vectors

As CMOS technology scaling continues into the nanoscale domain, static or leakage power consumption becomes a vital design parameter. This paper proposes methods for reducing leakage currents by controlling the input vector in nano-scale full adder cells operating in either active mode or standby mode. With proper input vector control, it is possible to obtain over 40% leakage power savings for most of the full adder circuits presented.

Reducing thermal hotspots in microprocessors with expanded component sizing

Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.

Use of increased transistor gate length for leakage reduction in caches

Leakage is a growing issue with the advancements of technologies. It is a predominant problem of on chip caches of microprocessors. The cache is a major portion of the microprocessor area. Further, the SRAM cell is a significant contributor of transistor leakage power. This paper analyses leakage-delay trade-off for increase of the transistor gate length in the on chip cache at 22nm, 32nm and 45nm technology nodes. In 45nm technology node a gain in leakage reduction of over 13.7% can be achieved with a penalty of 0.3% increase in delay by increasing the gate length by 1nm. Similarly leakage reduction of over 38% can be achieved with additional delay of 27.2% in 22nm technology.

Energy efficient lossless image compression with prediction-based transform

Image processing for compression is an area that has been widely explored especially after microprocessors and modern digital networks which has enabled large traffic between various electronic components. Images have become the preferred form of communication and needs to be compressed for efficient transmission. A lossless energy efficient image compression method is presented in this paper where the image is divided into quadrants. The remaining three quadrants are predicted based on the first quadrant and the error is calculated. The resulting first quadrant and the three error quadrants are compressed using Huffman coding. It is proposed to utilize multi-level processing of the image for high compression ratio. The overall power consumption for TIC6414 processor is estimated using CPU cycle count.

Topology-related effects of Gated-V dd and Gated-V ss techniques on full-adder leakage and delay at 65nm and 45 nm

Full-adders are used extensively in most types of digital computing systems. Any design decision made at the full-adder level is likely to have a significant impact on the speed or power consumption of the entire digital system. In this paper, we study how various full-adder topologies are affected by the Gated-Vdd and Gated-Vss techniques at 65 nm and 45 nm, from a leakage power-delay perspective. We observed that most of the circuits studied resulted in leakage-current savings of more than 80% with Gated-Vdd, incurring a small delay penalty. Delay penalty in case of Gated-Vdd is more that of Gated-Vss. In Gated-Vss, there is a wide variation in leakage power between the topologies studied.