Scott J. Butler

Static induction transistors optimized for high-voltage operation and high microwave power output

An optimized static induction transistor (SIT) design utilizing local oxidation in a self-aligned geometry is described. Devices with 10.5- and 7-µm pitch (gate-to-gate spacing), which have been optimized with respect to epitaxial layer thickness and resistivity, have attained a combination of operating frequency and breakdown voltage which is much higher than devices made with other technologies. The 10.5-µm pitch SITs have a blocking voltage of 170 V with 6-dB gain at 225 MHz and 10-dB gain at 900 MHz. Typical multicell power devices have demonstrated 110-W output power at 225 MHz with 65-percent drain efficiency and 25 W at 900 MHz with 40-percent drain efficiency, operated at voltages in excess of 100 V de bias. The 7-µm pitch SITs have a blocking voltage of 140 V and the same power gain performance at 225 and 900 MHz as the 10.5-µm pitch devices, but with higher effiency and a higher maximum frequency of operation. Typical multicell power devices of this type have achieve 110-W output power at 225 MHz with 70-percent drain efficiency and 25 W at 900 MHz with 55-percent drain efficiency operated at 90 V de bias.

Low temperature operation of UHF power static induction transistors

Abstract This paper describes the results of recent experiments with high power surface gate static induction transistors (SITs) operated at and near liquid nitrogen temperatures. The temperature dependence of important large signal and small signal device parameters over a wide range of operating temperatures is described. UHF power performance of liquid nitrogen cooled SIT power amplifiers is described as well. At 425 MHz, a single transistor power amplifier has been fabricated which exhibits output power levels > 350 W with 8 dB gain and nearly 80% drain efficiency. Smaller test devices have been used in an 850 MHz amplifier, which exhibits 30 W c.w. with 7.8 dB gain and 64% drain efficiency.