Scott J. Weber

A functional validation technique: biased-random simulation guided by observability-based coverage

We present a simulation-based semi-formal verification method for sequential circuits described at the register-transfer level. The method consists of an iterative loop where coverage analysis guides input pattern generation. An observability-based coverage metric is used to identify portions of the circuit not exercised by simulation. A heuristic algorithm then selects probability distributions for biased random input pattern generation that targets non-covered portions. This algorithm is based on an approximate analysis of the circuit modeled as a Markov chain at steady state. Node controllability and observability are estimated using a limited depth reconvergence analysis and an implicit algorithm for manipulating probability distributions and determining steady-state behavior. An optimization algorithm iteratively perturbs the probability distributions of the primary inputs in order to improve estimated coverage. The coverage enhancement achieved by our approach is demonstrated on benchmarks from the ISCAS89 and VIS suites.

Developing architectural platforms: a disciplined approach

The Mescal project brings a formalized, disciplined methodology to the design of programmable platform-based systems, enabling the exploration of a wide array of architectures and a correct-by-construction path to implementation.

Using minimal minterms to represent programmability

We address the problem of formally representing the programmability of a system. We define the programmability of a system as the set of valid execution paths that can be configured statically by software. We formally represent this programmability as a Boolean function. From this representation, we extract a subset of on-set minterms that we call minimal minterms. We prove that these minimal minterms represent the set of smallest schedulable atomic actions of the system, and that we can use a special generator relation to determine if subsets of these actions can be executed in parallel. We also prove that given an arbitrary Boolean function we can extract the minimal minterms and recreate the entire on-set by applying the generator relation to every element of the power set of the set of minimal minterms. Thus, the minimal minterms represent the complete instruction set supported by the system, and the generator relation represents the inherent parallelism among the instructions. Furthermore, we automatically generate the required software development tools and hardware implementation from this representation of programmability. Finally, we show that we can efficiently compute the minimal minterms and apply the generator relation to verify parallel executions on interesting data path systems.

Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express

In communication centric application domains flexible interfaces are required to support the variety of recently emerged and still evolving high-speed serial interconnect standards. To develop such interfaces, typical application scenarios have to be identified, and common functionality and specific characteristics of the selected standards need to be analyzed. The results of this analysis can then guide the exploration of the design space. In this paper, we present a methodology which is tailored to the characteristics of serial interconnects. We use Click models for analysis and abstraction of the communication protocols and explore flexible interfaces within a cycle-accurate architecture development framework. Our results show the feasibility of implementing a flexible interface on a packet engine similar to those used in network processors. Based on our findings, we believe that flexible interfaces will form a new family of building blocks for future Systems-on-Chip.

Chapter 13 – Sub-RISC Processors

Publisher Summary The concurrency implementation gap is a major impediment to deploying programmable platforms. Architectures that provide poor support for application concurrency requirements make this gap wide; ad hoc methodologies for programming concurrent applications make the gap difficult to cross. Designers must address both these issues to achieve good results. First, it is important to choose a basic block processing element that can support application-specific process-level, data-level, and datatype-level concurrency. Tiny Instructionset Processors and Interconnect (TIPI) sub-RISC processing elements (PEs) are a compelling choice because they provide the right balance between programmability and application specificity. This comes at a lower cost than typical processor architectures in terms of hardware resources and designer hours. Second, designers should take a disciplined approach to deploying concurrent applications. To program the PEs, we provide a deployment methodology called Cairn that provides multiple abstractions for the different facets of the design problem. This makes it easy to cross the implementation gap. Designers can experiment with changes to the application, the architecture, and the mapping individually. Effective design space exploration will lead to high performance. The performance numbers for FPGA test case implementation show the advantages of sub-RISC PEs. Implemented in an ASIC, a multiprocessor of ClickPE and LuleaPE elements can easily surpass the IXP2800 in raw packet destination lookup performance. Clearly, the PEs can make excellent building blocks for future programmable platforms.