Scott Luning

Advanced transistor structures for high performance microprocessors

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Physical characterization of two‐dimensional doping profiles for process modeling

Physical characterization of doping profiles in two dimensions holds great promise for both high quality analysis of specific structures and for general physical model verification. This latter activity enables the calibration of process simulators and could lead to accurate predictive simulation of modern integrated circuit devices. We used both one‐ and two‐dimensional analytical techniques [secondary‐ion‐mass spectroscopy (SIMS) and transmission electron microscopy (TEM)] to quantitatively characterize implanted and rapid‐thermal‐annealed dopant profiles at a polysilicon gate edge. The samples were given self‐aligned arsenic implants of 1×1015 ions/cm2 at 35 and 120 keV and at 0° and 20° angles of incidence. The implant was followed by a 30 s/1000 °C rapid thermal anneal. SIMS profiles were used to calibrate 1D simulations and the TEM micrographs in the 1D regions far from the mask edge. Quantitative TEM micrographs near the gate edge were then compared with two‐dimensional simulations of final doping ...

High Performance 65nm SOI Transistors Using Laser Spike Annealing

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating effect included) at 200nA/mum off-state current and VDD of 1.0V. PMOS drive current is enhanced by 5% to a value of 575muA/mum (60OmuA/mum if 5% PFET SOI self-heating effect included) which is less than enhancement observed in the NFET due to the differing amount of enhancement of capacitive inversion thickness (TINV) at short channel. With respect to circuit and product performance, this device provides a 5% delay improvement for a product-like ring-oscillator (RO) and results in an improved cross-die statistical distribution of RO delay time. The minimum stable SRAM operating voltage (Vmin) is also significantly improved, indicating that control of the overlap capacitance (Cov) may play a significant role in determining SRAM Vmin. For the first time, we report that the NFET Tinv reduction by LSA is substantially larger at shorter channel lengths which explains the large NFET drive current enhancements obtained by LSA

Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing

Dual stress liner process for high performance SOI CMOS technology at 32 nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32 nm gate length transistors.

Optimal Contact Placement in Partially Depleted SOI with Application to Raised Source-Drain Structures

We have studied the impact on drive current of bringing the S/D contacts closer to the gate edge. We found that there is an optimal location for contact placement beyond which Idsat decreases. The decrease in Idsat is due to two phenomena: i) current crowding and ii) increase in contact resistance. We show that raised S/D structure will be able to circumvent these problems and allow for further improvement in drive current.

Modeling and Extraction of Effective Lateral Doping Profile Using the Relation of On-Resistance vs. Overlap Capacitance in (100) and (110)-Oriented MOSFETs

A comprehensive technique for the accurate extraction of the effective lateral doping abruptness and the spreading resistance components is applied to both Si (100) and Si (110) MOSFETs. The spreading resistance components under extension-to-gate overlap and spacer regions are successfully correlated to the lateral extension (EXT) doping abruptness by the relationship between on-resistance (Ron) and overlap capacitance response (Cov). The lateral doping profile difference is extracted between (100) and (110) PMOS, which successfully explains higher external resistance in measured (110) PMOS.

HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 /spl mu/m CMOS technology

The results of an intensive study of drain engineering work to improve the hot carrier injection (HCI) reliability of N-channel MOSFETs in 0.25 /spl mu/m CMOS technology are presented. While an As/P LDD structure improved HCI by sacrificing off-current, an alternative method of integrating phosphorus into the heavy dose As S/D junction delivers an equivalent HCI lifetime and an even lower off-current. Around one order of magnitude of HCI lifetime enhancement has been achieved with this P-doping of the S/D. Device simulations supported our approach.