Scott R. Nelson

Leo: a system for cost effective 3D shaded graphics

A physically compact, low cost, high performance 3D graphics accelerator is presented. It supports shaded rendering of triangles and antialiased lines into a double-buffered 24-bit true color frame buffer with a 24-bit Z-buffer. Nearly the only chips used besides standard memory parts are 11 ASICs (of four types). Special geometry data reformatting hardware on one ASIC greatly speeds and simplifies the data input pipeline. Floating-point performance is enhanced by another ASIC: a custom graphics microprocessor, with specialized graphics instructions and features. Screen primitive rasterization is carried out in parallel by five drawing ASICs, employing a new partitioning of the back-end rendering task. For typical rendering cases, the only system performance bottleneck is that intrinsically imposed by VRAM.

Twelve characteristics of correct antialiased lines

Abstract Many papers have been written on line antialiasing algorithms. Most ignore important features that can leave visible artifacts. This paper presents 12 desirable characteristics of antialiased lines and discusses algorithmic trade-offs that affect each of the characteristics from a behavioral perspective. Accompanying color images show the differences between acceptable and unacceptable behavior for each characteristic. This paper provides the information needed to visibly analyze how well a particular antialiased line algorithm works.

High quality hardware line antialiasing

Abstract The graphics community has understood line antialiasing reasonably well for many years. Many papers have dealt with the subject, but none of them have offered a complete solution. This paper explains all of the details of a wellbehaved hardware algorithm used in the SparcStation ZX that, although imperfect, works very well in practice. The paper discusses trade-offs at each point and the reasoning that went into the decisions that were made.