Scott W. Crowder

Software defined environments: an introduction

During the past few years, enterprises have been increasingly aggressive in moving mission-critical and performance-sensitive applications to the cloud, while at the same time many new mobile, social, and analytics applications are directly developed and operated on cloud computing platforms. These two movements are encouraging the shift of the value proposition of cloud computing from cost reduction to simultaneous agility and optimization. These requirements (agility and optimization) are driving the recent disruptive trend of software defined computing, for which the entire computing infrastructure--compute, storage and network--is becoming software defined and dynamically programmable. The key elements within software defined environments include capability-based resource abstraction, goal-based and policy-based workload definition, and outcome-based continuous mapping of the workload to the available resources. Furthermore, software defined environments provide the tooling and capabilities to compose workloads from existing components that are then continuously and autonomously mapped onto the underlying programmable infrastructure. These elements enable software defined environments to achieve agility, efficiency, and continuous outcome-optimized provisioning and management, plus continuous assurance for resiliency and security. This paper provides an overview and introduction to the key elements and challenges of software defined environments.

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro

This embedded-DRAM macro is designed as a DRAM cache for a future gigahertz microprocessor system based on a logic-based DRAM technology. The most notable feature of this macro is its ability to run synchronously with a gigahertz CPU clock in a fully pipelined fashion. It is designed to operate with a 1-GHz clock signal at 85/spl deg/C, nominal process parameters, and a 10% degraded V/sub DD/. The design is fully pipelined and synchronous with 16 independent subarrays. With 1-kb wide I/0 and a 1-GHz clock, the maximum data rate becomes 1 Tb per second. The address access time is 3.7 ns, four cycles with a 1-GHz clock. The subarray cycle time is 12 ns.