Sean Keller

A transregional model for near-threshold circuits with application to minimum-energy operation

The most energy-efficient operating point for CMOS circuits is near the threshold voltage. Conventional models are difficult to use in this region because they are piecewise and/or discontinuous around threshold. This paper proposes a simple new model for Ion that is valid in the near-threshold region. Based on the ON-current, a propagation delay model is derived. The model is applied to determine the minimum energy point for inverter chains. The transregional model matches simulated data within 15 mV, while the conventional exponential subthreshold model underestimates the supply voltage by up to 80 mV.

A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

Power dissipation is currently one of the most important design constraints in digital systems. In order to reduce power and energy demands in the foremost technology, namely CMOS, it is necessary to reduce the supply voltage to near the device threshold voltage. Existing analytical models for MOS devices are either too complex, thus obscuring the basic physical relations between voltages and currents, or they are inaccurate and discontinuous around the region of interest, i.e., near threshold. This paper presents a simple transregional compact model for analyzing digital circuits around the threshold voltage. The model is continuous, physically derived (by way of a simplified inversion-charge approximation), and accurate over a wide operational range: from a few times the thermal voltage to approximately twice the threshold voltage in modern technologies.

A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits

This paper presents a proof that the adversary path timing assumption is both necessary and sufficient for correct SI circuit operation. This assumption requires that the delay of a wire on one branch of a fork be less than the delay through a gate sequence beginning at another branch in the same fork. Both the definition of the timing assumption and the proof build on a general, formal notion of computation given with respect to production rule sets. This underlying framework can be used for a variety of proof efforts or as a basis for defining other useful notions involving asynchronous computation.

Concurrent rewriting semantics and analysis of asynchronous digital circuits

Modern asynchronous digital circuits are highly concurrent systems composed largely of customized gates, and can be elegantly modeled using the language of production rules (PRs). One of the present limitations of the state of the art in asynchronous circuit design is that no formal executable semantics of asynchronous circuits has yet been given at the PR level. The primary contribution of this paper is to define, using rewriting logic and Maude, an executable formal semantics of asynchronous circuits at the PR level under three common timing assumptions. Our semantics provides a circuit designer with a PR-level circuit interpreter and with a decision procedure for checking key circuit properties, including hazard-freedom and deadlock-freedom. We describe several reductions and optimizations that can be used to reduce the state space of circuits in our formal semantics and investigate the impact of these reductions experimentally. The analysis scales up to circuits of over 100 PRs in spite of the high levels of concurrency involved.

Rewriting semantics of production rule sets

This paper is about the semantics of production rule sets, a language used to model asynchronous digital circuits. Two formal semantics are developed and proved equivalent: a set-theoretic semantics that improves upon an earlier effort of ours, and an executable semantics in rewriting logic. The set-theoretic semantics is especially suited to meta-level proofs about production rule sets, whereas the executable semantics can be used with existing tools to establish, automatically, desirable properties of individual circuits. Experiments involving several small circuits are detailed wherein the executable semantics and the rewriting logic tool Maude are used to automatically check two important properties: hazard and deadlock freedom. In doing so, we derive several useful optimizations that make automatic checking of these properties more tractable.

DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS

This paper describes DD1, an asynchronous radiation-hard 8-bit AVR® microcontroller (MCU) implemented in TSMC 40LP, a low-power bulk 40nm CMOS process. Designed for extreme reliability, DD1 uses quasi-delay-insensitive (QDI) asynchronous logic and contains full-custom radiation-hard memories and logic cells. The chip was found fully functional on first silicon over a range of operating voltages from near-threshold (500mV) to above the nominal VDD (1.1V). It qualifies as both ultra-low power (<;100μW/MHz) and radiation-hard by design. At 550mV the MCU operates at 1MIPS with a power consumption of 18μW/MIPS. At 1.1V it runs at 20MIPS consuming 75μW/MIPS (1.5mW total). After extensive testing, it was found to be total-dose and latch-up immune and has an upset immunity of 2E-6 SEE/device-day (CREME96 geosynchronous near-earth orbit).