Sebastian Wallner

Tree parity machine rekeying architectures

The necessity of securing the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e., small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronization of tree parity machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration, we evaluate characteristics of a standard-cell ASIC design realization as IP-core in 0.18/spl mu/-technology.

A configurable system-on-chip architecture for embedded and real-time applications: concepts, design and realization

This paper presents a Configurable System-on-Chip (CSoC) architecture that includes programmable and reconfigurable hardware to cope with the flexibility and real-time signal processing demands in future telecommunication and multimedia systems. A programmable micro Task Controller (mTC) with a small instruction set and a novel pipelined configuration technique with descriptors as configuration templates allows a dynamic use of physical processing resources. The CSoC architecture provides a micro-task based programming model, approves a library-based design approach to reduce developing time and costs and allows forward compatibility to other architecture families. It is shown to be easy scalable to future VLSI technologies where over a hundred processing cells on a single chip will be feasible to deal with the inherent dynamics of future applications and system requirements. Several mappings of commonly used signal processing algorithms and implementation results are given for a standard cell ASIC design realization in 0.18 µm 6-layer UMC CMOS technology.

Secure communication in microcomputer bus systems for embedded devices

The protection of the microcomputer bus system in embedded devices is essential to prevent eavesdropping and the growing number of todays hardware hacking attacks. This contribution presents a hardware solution to ensure microcomputer bus systems via the Tree Parity Machine Rekeying Architecture (TPMRA). For this purpose a scalable TPMRA IP-core is designed and implemented in order to meet adaptability, low cost terms and variable bus performance requirements. It allows the authentication of different bus participants as well as the encryption of chip-to-chip buses from a single primitive. The solution is transparent and easy applicable to an arbitrary microcomputer bus system for embedded devices on the market. A proof of concept implementation shows the applicability of the TPMRA in the standardized Advanced Microprocessor Bus Architecture (AMBA) by implementing the IP-core extension into the peripheral AMBA bus-to-bus interface. It will be shown that the proposed solution is latency free and can be easy implemented into the AMBA bus interface bridge in order to protect the ARM bus system with a low hardware overhead considering all AMBA bus features.

A Key Establishment IP-Core for Ubiquitous Computing

A most critical and complex issue with regard to constrained devices in the ubiquitous and pervasive computing setting is secure key exchange. The restrictions motivate the investigation and discussion of alternative solutions. We suggest a low hardware-complexity solution for authenticated symmetric key exchange, using a tree parity machine rekeying architecture. An authenticated key exchange is formulated from within the tree parity machine interaction concept and requires only few transmissions. It averts a man-in-the-middle attack and the currently known attacks on the non-numbertheoretic on principle. A key exchange can be performed within a few milliseconds, given typical limited bandwidth wireless communication channels. Characteristics of a standard-cell ASIC design realization as IP-core in 0.18mu-CMOS technology are evaluated

Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines

The protection of chip-level microcomputer bus systems in embedded devices is essential to prevent the growing number of hardware hacking attacks. This paper presents an authenticated key exchange and encryption solution in order to ensure chip-level microcomputer bus systems via the tree parity machine rekeying architecture (TPMRA). Due to this intention, a scalable TPMRA IP-core is designed and implemented in order to meet variable bus performance requirements. It allows the authentication of the bus participants as well as the encryption of chip-to-chip buses from a single primitive. The solution is transparent and easy applicable to an arbitrary microcomputer bus system for embedded devices on the market. A proof of concept implementation shows the applicability of the TPMRA in the standardized advanced microprocessor bus architecture (AMBA) by implementing the IP-core into the peripheral bus-to-bus interface (AHB-APB-bridge). It will be shown that the solution is latency free and can be used in order to protect the ARM bus system with a low hardware overhead considering all AMBA bus features.

Micro-Task Processing in Heterogeneous Reconfigurable Systems

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

Designing Low-Cost Cryptographic Hardware for Wired- or Wireless Point-to-Point Connections

Science and industry consider non classical cryptographic technologies to provide alternative security solutions. They are motivated by strong restrictions as they are often present in embedded security scenarios and in application such as battery powered embedded systems and RFID devices with often severe resource limitations. We investigate the implementation of a low hardware complexity cryptosystem for lightweight (authenticated) symmetric key exchange, based on two new Tree Parity Machine Rekeying Architectures (TPMRAs). This work significantly extends and optimizes (number of gates) previously published results on TPMRAs. We evaluate characteristics of standardcell ASIC design realizations as IP-core in 0.18-CMOS technology and an implementation into a standard bus controller with security features.