Sébastien Fregonese

Computationally Efficient Physics-Based Compact CNTFET Model for Circuit Design

We present a computationally efficient physics-based compact model designed for the conventional CNTFET featuring a MOSFET-like operation. A large part of its novelty lies on the implementation of a new analytical model of the channel charge. In addition, Boltzmann Monte Carlo (MC) simulation is performed with the challenge to cross-link this simulation technique to the compact modeling formulation. The comparison of the electrical characteristics obtained from the MC simulation and from the compact modeling demonstrates the compact model accuracy within its range of validity. Then, from a study of the CNT diameter dispersion for three technological processes, the compact model allows us to determine the CNTFET threshold voltage distribution and to evaluate the resulting dispersion of the propagation delay from the simulation of a ring oscillator.

Analysis of CNTFET physical compact model

On the basis of acquired knowledge, the paper present a DC compact model designed for the conventional CNTFET (C-CNTFET) featuring a doping profile similar to n-MOSFET. The specific enhancement lies on the implementation of a physical based calculation of the minima of energy conduction subbands. This improvement allows a realistic analysis of the impact of CNT helicity and radius on the DC characteristics. The purpose is to enable the circuit designers to challenge CNTFET potentialities for performing logical or analogical functionalities within complex circuits

Implementation of Tunneling Phenomena in a CNTFET Compact Model

This paper presents the implementation of band-to-band tunneling (BTBT) mechanisms into the compact model of a conventional carbon nanotube transistor FET featuring a MOSFET-like operation. Appropriate equations enable the calculation of the BTBT current as well as the charge pileup in the channel. To ensure the model accuracy and validate the equation set, the compact model simulation results are methodically compared with nonequilibrium Green function ones. Afterward, the investigations on the BTBT effects with respect to the figures of merits of the transistor and circuit have led to draw the conclusion that their impact is of utmost importance for large-signal analog and digital circuit designs. Neglecting the BTBT phenomena lead to an underestimation of more than 50% of the gate inverter delay and to an underestimation of power consumption of 30%. Finally, tradeoff recommendations between chirality and operating bias voltage are presented.

A self-aligned vertical HBT for thin SOI SiGeC BiCMOS

We demonstrate a 4-mask HBT module, which enables the integration of three high performance self-aligned SiGeC HBTs into a 0.13/spl mu/m SOI CMOS technology. Static and dynamic transistor characteristics are described and compared with simulation results and bulk device performances.

Implementation of Electron–Phonon Scattering in a CNTFET Compact Model

This paper presents an extension of a ballistic compact model to the case of nonballistic transport for the conventional carbon nanotube FET featuring a MOSFET-like operation. A large part of the novelty lies on the analytical implementation of acoustic phonon (AP) and optical phonon (OP) scattering mechanism. To carry out this implementation, some simplifications of the theoretical description are proposed while staying as close as possible to physics and keeping the high-speed simulation and good convergence capability of the compact model. The compact model simulation results are systematically compared and validated with respect to nonequilibrium Green function simulation results. Then, we have investigated the impact of AP and OP scattering on transistor figures of merit. Taking into account the scattering processes is of utmost importance for both analog and digital circuit designs, since neglecting the scattering leads to an overestimation of more than 70% of the main figures of merit and will mislead designers when optimizing the operating point for analog applications.

Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices

We present an original method to implement neuro-inspired supervised learning for a synaptic array based on carbon nanotube devices. The device characteristics required to implement on chip learning within a crossbar of carbon nanotube field effect transistors (CNTFETs) as synaptic arrays were experimentally demonstrated and accurately modeled through a specific electrical compact model. We performed electrical simulations of learning for an array of 24 nanotube memory devices corresponding to a 3 input × 3 output neural layer that revealed successful learning of separable logic functions within very few epochs, even when a realistic variability of nanotube diameter was taken into account. Such a learning approach opens the way to the use of high-density synaptic arrays as generic logic blocks in configurable circuits.

A compact model for SiGe HBT on thin-film SOI

Heterojunction bipolar transistor (HBT) fabrication on thin-film silicon-on-insulator (SOI) has been recently demonstrated. Due to the space volume constraint (thin film) for the device fabrication, the HBT structure is different from bulk HBT. In fact, compared to a bulk device, the buried layer has been suppressed and a lateral collector contact configuration is introduced. This device features a vertical expansion followed by a lateral expansion of the base-collector space charge region. This nonconventional charge behavior induces a kink in the base-collector junction capacitance characteristics, and as a consequence a modified Early effect. Furthermore, the low current transit time is modified compared to a bulk HBT. In this paper, all these effects are analyzed and a compact model for SOI-HBT is proposed. The model is validated on real SOI-HBTs with different collector doping levels.

Graphene Transistor-Based Active Balun Architectures

While different RF functionalities, such as an amplifier or a mixer, have been designed using the graphene FET (GFET) devices, the balun circuit has not been explored. In this paper, two innovative active balun architectures are presented taking advantage of the GFETs unique symmetrical and ambipolar behavior, respectively. The symmetry-based active balun circuit is realized using an advanced SiC-based GFET RF technology. After circuit design and optimization using a large signal GFET compact model, the circuit has been fabricated and characterized. Measurement results confirm its excellent functionality. Circuit simulation shows that the second architecture exploring the GFETs ambipolar behavior gives equivalent results compared with the first architecture. Both topologies avoid asymmetric impedance matching and result in the accurate amplitude and phase balance of the balun.

An Accurate Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature.

FPGA Design with Double-Gate Carbon Nanotube Transistors

Double-gate carbon nanotube field effect transistors (DGCNTFETs) are novel devices showing an interesting property allowing to control the p- or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on a compact physical model of these devices, we demonstrate the benefit of designing field-programmable gate arrays (FPGAs) using fine-grain DG-CNTFET logic blocs rather than traditional look-up tables and coarse-grain DG-CNTFET logic blocs. In particular, we show a reduction by 13% to 48% on average in terms of delay of FPGA benchmarks.