Sébastien Vieillard

Original Articles: Experimental design and genetic algorithm optimization of a fuzzy-logic supervisor for embedded electrical power systems

The embedded power systems are nowadays developing at high pace. Hybrid-electric vehicles, full-electric vehicles, airplanes, ships, high-speed trains, all share a common point - the embedded electrical power system. This paper aims to present an optimization methodology of a fuzzy-logic supervision strategy. The optimization objectives are to minimize the DC-link voltage variations, and to increase the system efficiency by reducing the dissipated power. For that, a methodology involving the experimental design and genetic algorithm will be presented. The simulation and experimental results are validating the proposed procedure.

Automatic layout optimization of a double sided power module regarding Thermal and EMC constraints

This paper presents an automatic layout process for power electronics integrated modules. The chip position and power layout is automatically generated according to the best EMC/Thermal trade off. Optimization techniques use simple but fairly accurate EMC and Thermal models, presented in this paper. The proposed method is illustrated on a 4 legs 2kW inverter used for aircraft applications. The realization will use double sided technology.

Minimization of Drain-to-Gate Interaction in a SiC JFET Inverter Using an External Gate-Source Capacitor

This paper presents a study on a SiC JFET leg of a 3-leg Voltage Source Inverter (VSI). The switching curves obtained with the JFET working in free wheeling mode are shown to point out drain-to-gate interaction effects. Indeed, during the drain-source voltage variations, the JFET gate-source voltage can have considerable variations, because of the electrical coupling induced by the gate-drain capacitance Cgd. When the gate-source voltage variation becomes too negative, there is a risk of occurrence of the phenomenon of punch-through in the gate-source junction. Conversely, when it is enough positive, the JFET may conduct and lead to a leg short-circuit. To decrease these undesired effects for the JFET legs and consequently for the SiC JFET inverter, an external gate-source capacitor is used. This solution is studied and optimized by simulation on an inverter leg.