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Dive into the research topics where Seiji Kameda is active.

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Featured researches published by Seiji Kameda.


IEEE Transactions on Neural Networks | 2003

An analog VLSI chip emulating sustained and transient response channels of the vertebrate retina

Seiji Kameda; Tetsuya Yagi

A silicon retina that emulates the sustained and the transient responses in the vertebrate retina was fabricated. The circuit of the chip consists of two layers of resistive network that have different length constants. The output emulating the sustained response possesses a Laplacian-Gaussian-like receptive field and, therefore, carries out a smoothing and contrast-enhancement on the input images. This receptive field was realized by subtracting voltages distributing over the two resistive networks. The output emulating the transient response was obtained by subtracting consecutive images that were smoothed out by the resistive network and is sensitive to moving objects. The outputs of these two channels can be obtained alternately from the silicon retina in real time, within time delays not exceeding a few tens of milliseconds, with indoor illumination. The outputs of the chip are offset-suppressed analog voltages since the uncontrollable mismatches of transistor characteristics are compensated for with the aid of sample/hold circuits embedded in each pixel circuit. The silicon retina fabricated in the present study can be readily used in current engineering applications, e.g., robot vision.


Systems and Computers in Japan | 1999

A parallel analog intelligent vision sensor with a variable receptive field

Tetsuya Yagi; Seiji Kameda; Kunihiko Iizuka

The retina is an intelligent vision sensor indispensable in real-time image information processing of animals. The parallel image processing function of the retina was realized in an analog CMOS integrated circuit (vision chip). The chip was implemented with a one-dimensional Laplacian–Gaussian receptive field the size of which can be controlled by external signals. Active pixel sensors were used in the sensor part of the chip where the light sensitivity can be controlled by varying the accumulation time. Circuits compensating for noise due to the mismatch of transistor characteristics were incorporated, and the experimental results verified that sufficiently accurate outputs can be obtained under natural illumination. The chip can effectively extract the spatial frequency bandwidth of the signal in the presence of noise.


international symposium on neural networks | 2003

An analog silicon retina with multi-chip configuration

Seiji Kameda; Tetsuya Yagi

The neuromorphic silicon retina is a novel analog very large scale integrated (VLSI) circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study. This silicon retina, however, has a trade-off problem between the resolution and the computational complexity as the neuromorphic silicon retina generally does, since the photo sensors and processing circuits are fabricated on a single-ship. To solve the problem, we have designed a multi-chip silicon retina in which the functional network circuits are divided into two chips, the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the chips are transferred to the H chip with analog voltages through line-parallel transfer bus. The sample/hold circuits embedded in the H chip compensate for the pattern noise generated on the transfer pathway. The number of pixels and the fill factor increased three times and twice as much as the previously fabricated chip, respectively.


IEEE Transactions on Neural Networks | 2011

Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy

Kazuhiro Shimonomura; Seiji Kameda; Atsushi Iwata; Tetsuya Yagi

A silicon retina is an intelligent vision sensor that can execute real-time image preprocessing by using a parallel analog circuit that mimics the structure of the neuronal circuits in the vertebrate retina. For enhancing the sensors robustness to changes in illumination in a practical environment, we have designed and fabricated a silicon retina on the basis of a computational model of brightness constancy. The chip has a wide-dynamic-range and shows a constant response against changes in the illumination intensity. The photosensor in the present chip approximates logarithmic illumination-to-voltage transfer characteristics as a result of the application of a time-modulated reset voltage technique. Two types of image processing, namely, Laplacian-Gaussian-like spatial filtering and computing the frame difference, are carried out by using resistive networks and sample/hold circuits in the chip. As a result of these processings, the chip exhibits brightness constancy over a wide range of illumination. The chip is fabricated by using the 0.25-μm complementary metal-oxide semiconductor image sensor technology. The number of pixels is 64 × 64, and the power consumption is 32 mW at the frame rate of 30 fps. We show that our chip not only has a wide-dynamic-range but also shows a constant response to the changes in illumination.


International Journal of Neural Systems | 1999

Real time image processing with an analog vision chip system.

Seiji Kameda; Akira Honda; Tetsuya Yagi

A linear analog network model is proposed to characterize the function of the outer retinal circuit in terms of the standard regularization theory. Inspired by the function and the architecture of the model, a vision chip has been designed using analog CMOS Very Large Scale Integrated circuit technology. In the chip, sample/hold amplifier circuits are incorporated to compensate for statistic transistor mismatches. Accordingly, extremely low noise outputs were obtained from the chip. Using the chip and a zero-crossing detector, edges of given images were effectively extracted in indoor illumination.


IEEE Transactions on Neural Networks | 2006

An analog silicon retina with multichip configuration

Seiji Kameda; Tetsuya Yagi

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study . The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.


international symposium on circuits and systems | 2003

A silicon retina system that calculates direction of motion

Seiji Kameda; Tetsuya Yagi

A silicon retina was fabricated to emulate two fundamental types of response in the vertebrate retinal circuit, namely the sustained and transient responses. The sustained response exhibits a Laplacian-Gaussian-like receptive field. The transient response is obtained by subtracting consecutive image frames. The outputs of the chip are offset-suppressed analog voltages since uncontrollable mismatches of transistor characteristics are compensated for with the aid of sample/hold circuits embedded in each pixel circuit. The chip was applied to extract direction of motion using FPGA in real-time under an indoor illumination.


systems man and cybernetics | 1999

An artificial retina with adaptive mechanisms and its application to retinal prosthesis

Tetsuya Yagi; Seiji Kameda; Yuki Hayashida; Liming Li

The retina is a paradigm of novel image processing systems in which a real time computation with low power dissipation and a compact hardware is required. The basic structure underlying the computation of outer retinal neural network was elucidated with physiological experiments and computer simulations. We describe the spatio-temporal properties of outer retinal circuit with an equivalent resistive circuit model. Based on the model, an artificial retina was fabricated using analog CMOS VLSI circuit technology. The output of artificial retina emulates the center-surround antagonistic receptive field. The chip was incorporated with light-adaptive functions, which are inspired by physiological observations, to extract edges of a given image effectively. Preliminary experiments of applying the artificial retina for robot vision as well as for retinal prosthesis are performed.


international symposium on circuits and systems | 2005

An image pre-processing system employing neuromorphic 100 x 100 pixel silicon retina

Ryotaro Takami; Kazuhiro Shimonomura; Seiji Kameda; Tetsuya Yagi; Silicon Retina

A 100/spl times/100 pixel analog silicon retina was fabricated. The two functions of the silicon retina were verified: a Laplacian-Gaussian-like spatial filtering and a subtraction of consecutive frames. The analog silicon retina fabricated in the present study has matured from a development prototype to full-scale practical usefulness. Furthermore, we have designed a pre-processing system that consists of the silicon retina and FPGA. The system has compact hardware and low power dissipation and therefore is suitable for robotic vision.


international conference of the ieee engineering in medicine and biology society | 2014

A multichannel current stimulator chip for spatiotemporal pattern stimulation of neural tissues.

Seiji Kameda; Yuki Hayashida; Yuta Tanaka; Dai Akita; Tetsuya Yagi

We developed a prototype very-large-scale integration chip of a multichannel current stimulator for stimulating neural tissues by utilizing 0.25 μm high-voltage complementary metal-oxide-semiconductor technology. Our designed chip has 20 output channels that are driven by five current buffers arranged in parallel; each buffer controls four output channels in time-sharing mode. The amplitude of a stimulation pulse can be controlled within a range of approximately ±100 μA/phase in each output channel. The stimulus parameters, e.g., amplitude and duration, are controlled separately for each channel by digital codes stored in built-in registers. Combinations of anode and cathode electrodes to pass the current can be changed online. We integrated our stimulator chip with a multielectrode array and studied the neuronal responses to multichannel current stimulations with various temporal patterns in mouse brain slices.

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Tetsuya Yagi

Kyushu Institute of Technology

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Keisuke Inoue

Kyushu Institute of Technology

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