Seishi Okada

A 1.3GHz fifth generation SPARC64 microprocessor

A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 37.4W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recovery mechanism is implemented for execution units and data path logic circuits in addition to on-chip arrays to detect and recover from data logic error. This processor is developed by using mostly in-house CAD tools.A fifth generation SPARC64 processor implemented in 130 nm CMOS process with 8 layers of Cu metallization operates with a 1.3 GHz clock and dissipates 34.7 W. The processor is a 4-issue out-of-order design with 2 MB on-chip level-2 cache. Error checking is added on the data-path in addition to memory. An instruction is retried for correction when an error is detected in the datapath.

High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar

A 170GB/S crossbar for a multiprocessor server is realized with 10 LSIs. High density and low power are achieved with a 1.333 Gb/s single-ended signal transmission, a driver using pre-emphasis, and a receiver using a data-synchronous scheme. The total bandwidth of the address crossbar LSI is 1.23Tb/s with 704 drivers and 352 receivers