Seiya Shibata

Advanced SystemBuilder: A tool set for multiprocessor design space exploration

This paper presents our integrated system-level design tool set, named Advanced SystemBuilder. Advanced SystemBuilder supports overall methodology for system design and design space exploration, and provides programming model of systems, automatic synthesis capabilities for FPGA-based prototyping, cosimulation and execution profiling. A case study of MPEG4 decoder design shows the effectiveness of the design space exploration methodology with Advanced SystemBuilder.

Fast design space exploration for mixed hardware-software embedded systems

The time spent to design mixed hardware-software embedded systems is proportioned to their complexity. We present a highly efficient method that make use of simulators in order to find a pareto-solution between execution time and hardware area for mixed hardware-software embedded systems. Our method generates the minimum possible number of mappings in order to reduce the number of simulations. The exploration starts with two system mappings as initial pareto-solution. Then it repeats three steps, the generation of mappings, the simulation of generated mappings, and the update of the pareto-solution with the results of simulations. The experimental results show that our method is notably efficient and is able to find a pareto-solution with few errors compared to the complete search method.

A Fast Performance Estimation Framework for System-Level Design Space Exploration

This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.

Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration

Embedded systems usually have strict resource and performance constraints. Designers often need to improve the system design so that the system satisfies those constraints. In such case, performance bottlenecks should be identified and improved effectively. In this paper, we present a method to identify performance bottlenecks. Our method automatically identifies not only the bottlenecks but also a list of improvement rates of bottlenecks that is necessary for the system to satisfy design constraints. With the list of improvement rates, designers easily consider how to improve the bottlenecks. A case study on AES encryption and decryption application shows effectiveness of our method.

Automatic communication synthesis with hardware sharing for design space exploration

In this paper, we present a hardware sharing method for design space exploration of multiprocessor embedded systems. In our prior work, we had developed a system-level design tool which automatically synthesizes communications among the processes. In this work, we have extended our tool so that the tool can automatically synthesize communications which realize sharing of hardware among different processes. With the tool, designers only need to change the mapping information for hardware sharing. Designers therefore can easily explore wider design space with hardware sharing. A case study shows the effectiveness of our hardware sharing method.

A case study on MPEG4 decoder design with SystemBuilder

This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named SystemBuilder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15fps performance with pipelined hardware implementation.

Automatic instrumentation of profilers for FPGA-based design space exploration

In the system-level design of MPSoCs (Multi-Processor System-on-a-Chips), system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including CPUs and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, a case study on MPEG4 decoder design was conducted.

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs

Parallel traffic simulation is a critical component in large-scale traffic simulations and real-time traffic simulations. Dividing workloads evenly to multi-cores and multi-machines is a challenge in parallel traffic simulations. Current researches focus on map decomposition algorithms. However, without effective workload estimation algorithms, map decomposition algorithms tend to output imbalanced partitions. This paper proposes an elliptical-shaped workload estimation algorithm. The main idea of the algorithm is to assign the computational cost of a vehicle to links in an ellipse, whose centers (or foci points) are the vehicles origin node and the destination node. The algorithm is evaluated on a test-bed using a mesoscopic traffic simulator on the Lower Westchester County network. Case studies show that the new algorithm reduces 36% of the estimation errors in current length of links based workload estimation algorithms.