Seng Oon Toh

Characterization of Dynamic SRAM Stability in 45 nm CMOS

Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Various dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with conventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability characterization architecture using pulsed word-lines is implemented in 45 nm CMOS to identify sources of variability, and their impact on SRAM stability. Static read margins were observed to overestimate failures by 10-100 X while static write margins failed to predict outliers in critical writeability. Critical writeability was demonstrated to exhibit an enhanced sensitivity to process variations, random telegraph noise (RTN), and negative bias temperature instability (NBTI), compared to static write margins.

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Reducing static random-access memory (SRAM) operational voltage (Vmin) can greatly improve energy efficiency, yet SRAM Vmin does not scale with technology due to increased process variability. Assist techniques have been shown to improve the operation of SRAM, but previous investigations of assist techniques at design time have either relied on static metrics that do not account for important transient effects or make specific assumptions about failure distributions. This paper uses importance sampling of dynamic failure metrics to quantify and analyze the effect of different assist techniques, array organization, and timing on Vmin at design time. This approach demonstrates that the most effective technique for reducing SRAM Vmin is the negative bitline write assist, resulting in a Vmin of 600 mV for a 28-nm LP process in the typical corner.

Dynamic SRAM stability characterization in 45nm CMOS

A method for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins were observed to overestimate failures by up to 1000x while static write margins failed to predict outliers in dynamic write stability. Dynamic write stability was demonstrated to exhibit an enhanced sensitivity to process variations, and negative bias temperature instability (NBTI), compared to static write margins.

Analysis of the relationship between random telegraph signal and negative bias temperature instability

Random telegraph signal (RTS) is shown to be an intrinsic component of the shift in MOSFET threshold voltage (Vth) due to bias temperature instability (BTI). This is done by starting from a well-known model for negative BTI (NBTI), to derive the formula for RTS-induced Vth shift. Based on this analysis, RTS simply contributes an offset in NBTI degradation, with an acceleration factor that is dependent on the gate voltage and temperature. This is verified by 3-dimensional (3-D) device simulations and measurements of 45 nm-node bulk-Si PMOS transistors. It has an important implication for design of robust SRAM arrays in the future: design margin for RTS should not be simply added, because it is already partially accounted for within the design margin for NBTI degradation.

Impact of random telegraph signals on V min in 45nm SRAM

An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10× and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45 nm SRAM transistor Ids and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fail bit rate of SRAM with RTS is estimated using a statistical model populated by Iwrite measurements. Statistical analysis indicates a Vmin degradation of less than 50 mV due to RTS.

Technology Variability From a Design Perspective

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design.

SRAM stability characterization using tunable ring oscillators in 45nm CMOS

SRAM yield is often characterized through distributions of static read or write margins [1] [2]. These measurements are analog and therefore can be slow and provide a limited dataset. Distributions of per-cell minimum operating voltages can be characterized rapidly, however, and are often taken as a proxy to static noise margins. Both methods have a common limitation in that the characterization is done statically, thus ignoring any possible effects that may affect dynamic operation. Pulsed ring oscillators for evaluating SRAM cell read timing have been previously proposed [3]. In contrast, tunable ring oscillators (RO) for characterizing dynamic cell stability during write and read operations without the need to modify the SRAM array are demonstrated in this work. The performance variation is captured as a spread in RO operating frequencies and therefore can be obtained rapidly.

Parameter-specific ring oscillator for process monitoring at the 45 nm node

Parameter-specific ring oscillator (RO) experimental results are reported, demonstrating the ability to electronically distinguish and quantify sources of variations from gate lithography focus, gate-to-active overlay, nitride contact etch stop layer (CESL) strain, and Shallow Trench Isolation (STI) stress. A 2% RO frequency change due to gate focus variations, a three-four nm overlay error, a 20% increase in RO frequency per 1 um increase in length of diffusion (LOD), and a 3% speed-up per 0.3 um change in STI width are measured. Typical standard-deviation/mean (σ/μ) among 36 ROs within-chip is 0.2–0.3%.

Technology variability from a design perspective

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design.

Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28nm UTBB FD-SOI

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120μm2) single p-well (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. The results from a 140kb programmable dynamic SRAM characterization test module provide both information about location and cause of failures as well as power and performance by mimicking system operating conditions over a wide supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with a leakage current close to 100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.