Seok-Bum Ko

Efficient hardware implementation of an image compressor for wireless capsule endoscopy applications

The paper presents an area- and power-efficient implementation of an image compressor for wireless capsule endoscopy application. The architecture uses a direct mapping to compute the two-dimensional discrete cosine transform which eliminates the need of transpose operation and results in reduced area and low processing time. The algorithm has been modified to comply with the JPEG standard and the corresponding quantization tables have been developed and the architecture is implemented using the CMOS 0.18um technology. The processor costs less than 3.5k cells, runs at a maximum frequency of 150 MHz, and consumes 10 mW of power. The test results of several endoscopic colour images show that higher compression ratio (over 85%) can be achieved with high quality image reconstruction (over 30 dB).

A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

In this work we propose a high performance elliptic curve cryptographic processor over GF(2^1^6^3) for the applications that require high performance. It has three finite field (FF) RISC cores and a main controller to achieve instruction-level parallelism (ILP) for elliptic curve point multiplication. Customized instructions are proposed to decrease clock cycles. The interconnection among three FF cores and the main controller is obtained based on the analysis of both data dependency and critical path. The proposed design can reach 185MHz with 20,807 slices when implemented on Xilinx XC4VLX80 FPGA device and 263MHz with 217,904 gates when synthesized with TSMC .18@mm CMOS technology.

High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings

The decimal multiplication is one of the most important decimal arithmetic operations which have a growing demand in the area of commercial, financial, and scientific computing. In this paper, we propose a parallel decimal multiplication algorithm with three components, which are a partial product generation, a partial product reduction, and a final digit-set conversion. First, a redundant number system is applied to recode not only the multiplier, but also multiples of the multiplicand in signed-digit (SD) numbers. Furthermore, we present a multioperand SD addition algorithm to reduce the partial product array. Finally, a digit-set conversion algorithm with a hybrid prefix network to decrease the number of the logic gates on the critical path is discussed. An analysis of the timing delay and an HDL model synthesized under 90 nm technology show that by considering the tradeoff of designs among three components, the overall delay of the proposed 16 × 16-digit multiplier takes about 11 percent less timing delay with 2 percent less area compared to the current fastest design.

Noninvasive cuffless blood pressure estimation using pulse transit time and Hilbert-Huang transform

It is widely accepted that pulse transit time (PTT), from the R wave peak of electrocardiogram (ECG) to a characteristic point of photoplethysmogram (PPG), is related to arterial stiffness, and can be used to estimate blood pressure. A promising signal processing technology, Hilbert-Huang transform (HHT), is introduced to analyze both ECG and PPG data, which are inherently nonlinear and non-stationary. The relationship between blood pressure and PTT is illustrated, and the problems of calibration and re-calibration are also discussed in this paper. Moreover, multi-innovation recursive least square algorithm is employed to update the unknown parameter vector for the model and improve the results. Our algorithm is tested based on the continuous data from MIMIC database, and the accuracy is calculated to validate the proposed method.

A Fall and Near-Fall Assessment and Evaluation System

The FANFARE (Falls And Near Falls Assessment Research and Evaluation) project has developed a system to fulfill the need for a wearable device to collect data for fall and near-falls analysis. The system consists of a computer and a wireless sensor network to measure, display, and store fall related parameters such as postural activities and heart rate variability. Ease of use and low power are considered in the design. The system was built and tested successfully. Different machine learning algorithms were applied to the stored data for fall and near-fall evaluation. Results indicate that the Naïve Bayes algorithm is the best choice, due to its fast model building and high accuracy in fall detection.

A Study on the Floating-Point Adder in FPGAS

FPAGs are increasingly being used to design high-end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing standard, LOP, and far and close data-path floating-point addition algorithms. Each algorithm has complex sub-operations which lead significantly to overall latency of the design. Each of the sub-operation is researched for different implementations and then synthesized onto a Xilinx Virtex2p FPGA device to be chosen for best performance. According to our results, standard algorithm is the best implementation with respect to area but has overall large latency of 27.059 ns while occupying 541 slices. LOP algorithm improves latency by 6.5% on added expense of 38% area compared to standard algorithm. Far and close data-path implementation shows 19% improvement in latency on added expense of 88% in area compared to standard algorithm

A Study on Machine Learning Algorithms for Fall Detection and Movement Classification

Falls among the elderly is an important health issue. Fall detection and movement tracking are therefore instrumental in addressing this issue. This paper responds to the challenge of classifying different movements as a part of a system designed to fulfill the need for a wearable device to collect data for fall and near-fall analysis. Four different fall trajectories (forward, backward, left and right), three normal activities (standing, walking and lying down) and near-fall situations are identified and detected. Different machine learning algorithms are compared and the best one is used for real time classification. The comparison is made using Waikato Environment for Knowledge Analysis (WEKA), one of the most popular machine learning software. The system also has the ability to adapt to the different gait characteristics of each individual. A feature selection algorithm is also introduced to reduce the number of features required for the classification problem.

Design tradeoff analysis of floating-point adders in FPGAs

With gate counts of ten million, field-programmable gate arrays (FPGAs) are becoming suitable for floating-point computations. Addition is the most complex operation in a floating-point unit and can cause major delay while requiring a significant area. Over the years, the VLSI community has developed many floating-point adder algorithms aimed primarily at reducing the overall latency. An efficient design of the floating-point adder offers major area and performance improvements for FPGAs. Given recent advances in FPGA architecture and area density, latency has become the main focus in attempts to improve performance. This paper studies the implementation of standard; leading-one predictor (LOP); and far and close datapath (2-path) floating-point addition algorithms in FPGAs. Each algorithm has complex sub-operations which contribute significantly to the overall latency of the design. Each of the sub-operations is researched for different implementations and is then synthesized onto a Xilinx Virtex-II Pro FPGA device. Standard and LOP algorithms are also pipelined into five stages and compared with the Xilinx IP. According to the results, the standard algorithm is the best implementation with respect to area, but has a large overall latency of 27.059 ns while occupying 541 slices. The LOP algorithm reduces latency by 6.5% at the cost of a 38% increase in area compared to the standard algorithm. The 2-path implementation shows a 19% reduction in latency with an added expense of 88% in area compared to the standard algorithm. The five-stage standard pipeline implementation shows a 6.4% improvement in clock speed compared to the Xilinx IP with a 23% smaller area requirement. The five-stage pipelined LOP implementation shows a 22% improvement in clock speed compared to the Xilinx IP at a cost of 15% more area.

Bandwidth-aware routing and admission control for efficient video streaming over MANETs

In this paper, we develop and evaluate an adaptive self-configurable routing framework that can deal with dynamic nature of mobile ad hoc networks and provides quality-of-service (QoS) guarantees for efficient video streaming. Proposed framework mainly consists of two major components. Firstly, it is a reactive bandwidth-aware node-disjoint multipath routing protocol which determines routes based on the specified bandwidth requirements of the requesting application. The second component of the framework is a session admission control (SAC) process that permits or denies a session to enter into the network based on the current availability of network bandwidth. We also propose methods to handle QoS violations caused by network mobility and congestion by keeping backup routes, performing local route recovery, avoiding routing through short-lived low quality links and periodic monitoring of the active transmission routes. To verify our proposed algorithms, the network with H.264/SVC encoded video traces which are generated from real-time video traffic is used for modeling the behaviour of the source nodes. It has been observed that reactively discovered and maintained routes on the basis of the most recent information about network topology and available resources can significantly improve the admission decision accuracy of SAC process, in turn improving the quality of received video traffic significantly.

A 32-bit Decimal Floating-Point Logarithmic Converter

This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calculate accurate logarithms of 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. Redundant digit e1 is obtained by look-up table in the first iteration and the rest redundant digits ej are selected by rounding the scaled remainder during the succeeding iterations. The sequential architecture of the proposed 32-bit DFP logarithmic converter is implemented on Xilinx Virtex-II Pro P30 FPGA device and then synthesized with TMSC 0.18-um standard cell library. The implementation results indicate that the maximum frequency of the proposed architecture is 47.7 MHz in FPGA and 107.9 MHz in TMSC 0.18-um technology. The faithful 32-bit DFP logarithm results can be obtained in 18 cycles.