Seok Jun Lee

Area-efficient high-throughput MAP decoder architectures

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.

Linear turbo equalization analysis via BER transfer and EXIT charts

In this paper, two analytical methods are presented to investigate the soft information evolution characteristics of a soft-input soft-output (SISO) linear equalizer and its application to the design of turbo equalization systems without the reliance on extensive simulation. Given the channel and a SISO equalization algorithm, one method explored is to analytically compute the bit-error rate (BER) of the SISO equalizer in two extreme cases (no and perfect a priori information) from which a BER transfer characteristic is estimated. The second approach is to compute the mutual information [a key parameter of the extrinsic information transfer (EXIT) chart] at the two end points of the EXIT function. Then, by modeling the SISO equalizer BER transfer and EXIT functions as linear, some of the behavior of linear turbo equalization, such as how the BER performance can be improved as iterations proceed, can be predicted. Further, soft information evolution characteristics of different linear SISO equalizers can be compared and the usefulness of iterative methods such as linear turbo equalization for a given channel can be determined. Compared with existing methods for generating EXIT functions, these predictive methods provide insight into the iterative behavior of linear turbo equalizers with substantial reduction in numerical complexity.

A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.

Energy-efficient soft error-tolerant digital signal processing

In this paper, we present energy-efficient soft error (SE)-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs an low-complexity estimator of a main DSP block to guarantee reliability in presence of soft errors either in the MDSP or the estimator. For FIR filtering, it is shown that the proposed technique provides robustness to soft error rates of up to P/sub er/=10/sup -2/ in single-event upset (SEU). It is also shown that the proposed techniques provide 40%/spl sim/61% savings in power dissipation over that achieved via triple modula redundancy (TMR) when the desired signal-to-noise ratio SNR/sub des/=25/spl sim/35 dB.

A low-power VLSI architecture for turbo decoding

Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1.) computation between blocks are independent, 2.) a block can be segmented into computationally independent sub-blocks, and 3.) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50% - 84% with an area overhead of 14% - 70%. Subsequent application of voltage scaling results in up to 65% savings in power for block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20% - 44% for a block-interleaving depth of 2 in 0.25μm CMOS process.

Analysis of linear turbo equalizer via EXIT chart

We propose a method for the analysis of linear turbo equalization based on extrinsic information transfer (EXIT) charts. Given channel knowledge, and therefore the optimum linear equalizer coefficients, the evolution of soft information of the soft-input soft-output (SISO) equalizer can be estimated by computing bit error rates (BER) analytically. Compared to conventional analysis methods, the proposed method predicts the linear turbo equalizer performance without running extensive simulations to obtain the SISO equalizer EXIT charts. Using an empirically generated SISO decoder EXIT chart, convergence analysis can be undertaken. Further, the method provides a bound on the achievable BER for given channels and an estimate of equalizer complexity. These approximate analyses are validated via computer simulations.

Low-power turbo equalizer architecture

In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% /spl sim/ 59% and 8% /spl sim/ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% /spl sim/ 47% with negligible degradation in BER.

Switching LMS linear turbo equalization

Turbo equalization using linear filters for data detection has been shown to perform nearly as well as those based on the original maximum a posteriori probability (MAP) detection approach. Such linear equalization methods have taken on many forms in the literature, from simple least-mean-square (LMS)-based adaptive filtering approaches, to minimum mean square error (MMSE)-based methods that are recursively computed for each output symbol for each iteration. In this paper, we consider a class of turbo equalization algorithms in which complexity requirements dictate that a fixed set of filter coefficients must be used for all symbols and for all iterations. By computing one such set of coefficients via the LMS algorithm assuming unreliable soft information, and another set assuming highly reliable soft information, we show that a switching strategy can be employed, nearly achieving the performance of recomputing the coefficients at each iteration.

Convergence analysis for linear turbo equalization

In this paper, we propose a method for the analysis of linear turbo equalization that makes use of extrinsic information transfer (EXIT) charts. Given the channel knowledge and a time-invariant set of linear equalizer coefficients, the evolution of soft information in the soft-input soft-output (SISO) equalizer can be estimated via analytically measuring the mutual information between the transmitted symbols and their estimated a priori values at the two end points of an EXIT chart. Using this estimated equalizer EXIT chart and an empirically generated decoder EXIT chart, convergence analysis can be undertaken. In comparison with existing EXIT chart based methods, the proposed approach can significantly reduce the reliance on extensive computer simulation.

Switching methods for linear turbo equalization

In this paper, several switching methods are presented for a class of switching turbo equalization, where the performance improvement is achieved via adapting the choice of equalizers during the iterative procedure. Four techniques for equalizer selection are presented and compared in computer simulations. The switching scheme based on the average soft information provided by SISO decoders showed the best bit error rate (1.5 dB processing gain at 10/sup -4/) with low complexity.