Seokwoo Lee

Razor: circuit-level correction of timing errors for low-power operation

Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. We present a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins

A self-tuning DVS processor using delay-error detection and correction

In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18/spl mu/m technology. The processor employs delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1 % targeted error rate at a fixed frequency of 120MHz.

Circuit-aware architectural simulation

Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, the recent trend in system design toward architectures that react to circuit-level phenomena has outstripped the capabilities of traditional cycle-based architectural simulators. In this paper, we present an architectural simulator design that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics (such as latency,energy,or current draw) on a cycle-by-cycle basis. While these additional capabilities slow simulation speed, we show that the careful application of circuit simulation optimizations and simulation sampling techniques permit high levels of detail with sufficient speed to examine entire workloads.

A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction

In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18mum technology. The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1% targeted error rate at a fixed frequency of 120MHz

Robust Security Design

We consider the optimal contract between an entrepreneur and investors in a single-period model when both parties have limited liability, are risk-neutral toward cash flow risk, and are ambiguity-averse. Ambiguity aversion is modeled by multiplier preferences for robustness toward model uncertainty, as in Hansen and Sargent (2001). Efficient ambiguity-sharing implies that the first-best contract consists of either convertible debt or levered equity. As is customary, in the second-best contract, moral hazard is alleviated by giving more cash to investors in low cash flow states. Under many settings in our model, the optimal security has an equity-like component in high cash flow states, providing a contrast to the results in Innes (1990).