Seong-hun Jeong

Case Study: Verification Framework of Samsung Reconfigurable Processor

The SRP (Samsung Reconfigurable Processor) is a high-performance, low-power digital signal processor that supports two different operating modes: the VLIW (very long instruction word) mode for running control-intensive code and the CGA (coarse-grained reconfigurable array) mode for running computation-intensive code. In the SRP, an application starts in the VLIW mode, and then may switch back and forth many times between the CGA mode and the VLIW mode throughout its lifetime. In order to support this switching back and forth seamlessly, our C compiler for SRP is capable of generating an executable binary that contain codes for both VLIW and CGA modes. The unusual complexity of SRP verification originates from the unconventional processor architecture/micro-architecture and the complexity of our compiler. In order to manage the unconventional burden that confronts SRP verification engineers, we have aimed to build a scalable verification framework that is both flexible and efficient. In this paper, we report our experience so far, including our effort to be systematic and thorough in our approach.

Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System

The Samsung reconfigurable processor (SRP) is developed to accelerate multimedia applications such as video decoding, audio decoding, and image processing. Owing to coarse-grained reconfigurable array (CGRA) acceleration via software (SW) pipelining and application-specific intrinsic instructions, SRP outperforms other digital signal processors (DSPs) in these application domains. In addition, recent video systems include not only the SRP core but also hardware (HW) accelerators, coupled with demand for better performance. Consequently, the system becomes very complex. and the difficulty of debugging the system increases. Here we propose a hierarchical verification framework for the SRP video system. This approach, coupled with a proper verification plan, not only boosts the verification time for various aspects of the video system (e.g., CGRA specific features), but also helps to achieve verification closure without any verification holes.